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Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Article DOI: 10.3791/52711-v • 11:42 min • July 24th, 2015
July 24th, 2015 •
1,2, 1, 1, 1, 1, 1,3, 1, 1, 1, 1, 1, 4, 4, 1,5,6, 1,5,6, 1,5,6
1Department of Physics, University of California at Berkeley, 2Department of Chemistry, University of California at Berkeley, 3Department of Chemical and Biomolecular Engineering, University of California at Berkeley, 4National Institute for Materials Science (Japan), 5Materials Sciences Division, Lawrence Berkeley National Laboratory, 6Kavli Energy NanoSciences Institute, University of California at Berkeley and Lawrence Berkeley National Laboratory

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This paper details the fabrication process of a gate-tunable graphene device, decorated with Coulomb impurities for scanning tunneling microscopy studies. Mapping the spatially dependent electronic structure of graphene in the presence of charged impurities unveils the unique behavior of its relativistic charge carriers in response to a local Coulomb potential.

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Fabrication Gate-tunable Graphene Devices Scanning Tunneling Microscopy Coulomb Impurities Graphene Electronic Devices Charge Carriers Potentials Scanning Tunneling Spectroscopy Spatial Dependence Energy Dependence Hybrid Impurity-graphene Device Controlled Deposition Back-gated Graphene Surface Electronic Properties Electrostatic Gating Charge Carrier Density Molecular States Individual Coulomb Impurities STM/STS Studies Underlying Physics Hybrid Graphene Devices
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