Close-Space Sublimation-Deposited Ultra-Thin CdSeTe/CdTe Solar Cells for Enhanced Short-Circuit Current Density and Photoluminescence

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Summary

This work describes the complete fabrication process of thin absorber cadmium selenium telluride/cadmium telluride photovoltaic devices for enhanced efficiency. The process utilizes an automated in-line vacuum system for close-space sublimation deposition that is scalable, from fabrication of small area research devices as well as large-scale modules.

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Bothwell, A. M., Drayton, J. A., Jundt, P. M., Sites, J. R. Close-Space Sublimation-Deposited Ultra-Thin CdSeTe/CdTe Solar Cells for Enhanced Short-Circuit Current Density and Photoluminescence. J. Vis. Exp. (157), e60937, doi:10.3791/60937 (2020).

Abstract

Developments in photovoltaic device architectures are necessary to make solar energy a cost-effective and reliable source of renewable energy amidst growing global energy demands and climate change. Thin film CdTe technology has demonstrated cost-competitiveness and increasing efficiencies due partially to rapid fabrication times, minimal material usage, and introduction of a CdSeTe alloy into a ~3 μm absorber layer. This work presents the close-space sublimation fabrication of thin, 1.5 µm CdSeTe/CdTe bilayer devices using an automated in-line vacuum deposition system. The thin bilayer structure and fabrication technique minimize deposition time, increase device efficiency, and facilitate future thin absorber-based device architecture development. Three fabrication parameters appear to be the most impactful for optimizing thin CdSeTe/CdTe absorber devices: substrate preheat temperature, CdSeTe:CdTe thickness ratio, and CdCl2 passivation. For proper sublimation of the CdSeTe, the substrate temperature prior to deposition must be ~540 °C (higher than that for CdTe) as controlled by dwell time in a preheat source. Variation in the CdSeTe:CdTe thickness ratio reveals a strong dependence of device performance on this ratio. The optimal absorber thicknesses are 0.5 μm CdSeTe/1.0 μm CdTe, and non-optimized thickness ratios reduce efficiency through back-barrier effects. Thin absorbers are sensitive to CdCl2 passivation variation; a much less aggressive CdCl2 treatment (compared to thicker absorbers) regarding both temperature and time yields optimal device performance. With optimized fabrication conditions, CdSeTe/CdTe increases device short-circuit current density and photoluminescence intensity compared to single-absorber CdTe. Additionally, an in-line close-space sublimation vacuum deposition system offers material and time reduction, scalability, and attainability of future ultra-thin absorber architectures.

Introduction

Global energy demand is quickly accelerating, and the year 2018 demonstrated the fastest( 2.3%) growth rate in the last decade1. Paired with increasing awareness of the effects of climate change and the burning of fossil fuels, the need for cost-competitive, clean, and renewable energy has become abundantly clear. Of the many renewable energy sources, solar energy is distinctive for its total potential, as the amount of solar energy that reaches earth far exceeds global energy consumption2.

Photovoltaic (PV) devices directly convert solar energy to electrical power and are versatile in scalability (e.g., personal use mini-modules and grid-integrated solar arrays) and material technologies. Technologies such as multi- and single-junction, single-crystal gallium arsenide (GaAs) solar cells have efficiencies reaching 39.2% and 35.5%, respectively3. However, fabrication of these high efficiency solar cells is costly and time-consuming. Polycrystalline cadmium telluride (CdTe) as a material for thin film PVs is advantageous for its low cost, high-throughput fabrication, variety of deposition techniques, and favorable absorption coefficient. These attributes make CdTe propitious for large- scale manufacturing, and improvements in efficiency have made CdTe cost-competitive with PV-market-dominant silicon and fossil fuels4.

One recent advancement that has driven the increase in CdTe device efficiency is the incorporation of cadmium selenium telluride (CdSeTe) alloy material into the absorber layer. Integrating the lower ~1.4 eV band gap CdSeTe material into a 1.5 eV CdTe absorber reduces the front band gap of the bilayer absorber. This increases the photon fraction above the band gap and thus improves current collection. Successful incorporation of CdSeTe into absorbers that are 3 μm or thicker for increased current density has been demonstrated with various fabrication techniques (i.e., close-space sublimation, vapor transport deposition, and electroplating)5,6,7. Increased room temperature photoluminescence emission spectroscopy (PL), time-resolved photoluminescence (TRPL), and electroluminescence signals from bilayer absorber devices5,8 indicate that in addition to increased current collection, the CdSeTe appears to have better radiative efficiency and minority carrier lifetime, and a CdSeTe/CdTe device has a larger voltage relative to the ideal than with CdTe only. This has largely been attributed to selenium passivation of bulk defects9.

Little research has been reported on the incorporation of CdSeTe into thinner (≤1.5 μm) CdTe absorbers. We have therefore investigated the characteristics of thin 0.5 μm CdSeTe/1.0 μm CdTe bilayer-absorber devices fabricated by close-space sublimation (CSS) to determine whether the benefits seen in thick bilayer absorbers are also attainable with thin bilayer absorbers. Such CdSeTe/CdTe absorbers, more than twice as thin as their thicker counterparts, offer a notable decrease in deposition time and material and lower manufacturing costs. Finally, they hold potential for future device architecture developments which require absorber thicknesses of less than 2 μm.

CSS deposition of absorbers in a single automated in-line vacuum system offers many advantages over other fabrication methods10,11. Faster deposition rates with CSS fabrication boosts device throughput and promotes larger experimental datasets. Additionally, the single vacuum environment of the CSS system in this work limits potential challenges with absorber interfaces. Thin-film PV devices have many interfaces, each of which can act as a recombination center for electrons and holes, thus reducing the overall device efficiency. The use of a single vacuum system for the CdSeTe, CdTe, and cadmium chloride (CdCl2) depositions (necessary for good absorber quality12,13,14,15,16) can produce a better interface and reduce interfacial defects.

The in-line automated vacuum system developed at Colorado State University10 is also advantageous in its scalability and repeatability. For example, deposition parameters are user-set, and the deposition process is automated such that the user does not need to make adjustments during absorber fabrication. Although small area research devices are fabricated in this system, the system design can be scaled up for larger area depositions, enabling a link between research-scale experimentation and module-scale implementation.

This protocol presents the fabrication methods used to manufacture 0.5-μm CdSeTe/1.0-μm CdTe thin-film PV devices. For comparison, a set of 1.5 μm CdTe devices are fabricated. Single and bilayer absorber structures have nominally identical deposition conditions in all process steps, excluding the CdSeTe deposition. To characterize whether thin CdSeTe/CdTe absorbers retain the same benefits demonstrated by their thicker counterparts, current density-voltage (J-V), quantum efficiency (QE), and PL measurements are performed on the thin single and bilayer absorber devices. An increase in short-circuit current density (JSC) as measured by J-V and QE, in addition to an increase in PL signal for the CdSeTe/CdTe vs. CdTe device, indicate that thin CdSeTe/CdTe devices fabricated by CSS show notable improvement in current collection, material quality, and device efficiency.

Although this work focuses on the benefits associated with the incorporation of a CdSeTe alloy into a CdTe PV device structure, the complete fabrication process for CdTe and CdSeTe/CdTe devices is described subsequently in full. Figure 1A,B shows completed device structures for CdTe and CdSeTe/CdTe devices respectively, comprised of a transparent conducting oxide (TCO)-coated glass substrate, n-type magnesium zinc oxide (MgZnO) emitter layer, p-type CdTe or CdSeTe/CdTe absorber with CdCl2 treatment and copper doping treatment, thin Te layer, and nickel back contact. Excluding the CSS absorber deposition, the fabrication conditions are identical between the single and bilayer structure. Thus, unless otherwise noted, each step is performed on both CdTe and CdSeTe/CdTe structures.

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Protocol

CAUTION: Gloves must be worn when handling substrates to prevent film contamination and material-to-skin contact. This fabrication process requires the handling of structures containing cadmium compounds; therefore, a lab coat and gloves should be worn in the lab at all times.

1. Substrate cleaning

  1. Place TCO-coated glass substrates (9.1 cm x 7.8 cm) in a stainless steel rack with ample spacing such that cleaning solution and compressed air can be applied to each glass face.
  2. Blow any dust off the substrates using a nitrogen compressed air hose.
  3. Place the rack in an ultrasonic cleaner (UC1) and fill with isopropyl alcohol (IPA). Let sit for 30 min to remove residual oil and contaminants from the industrial glass cutting process.
  4. Drain the IPA from UC1. The IPA can be reused up to 5x for the initial cleaning of substrates.
  5. Rinse the substrates with deionized (DI) water, then fill UC1 with DI water about 1 cm above the top edge of the substrates. Add 200 mL of concentrated cleaning solution uniformly across the substrates to further remove residual oil, grease, particulates, or hard water stains.
  6. Using the main power, turn on UC1 to 43 kHz ultrasonic frequency and 425 W power and let the substrates sit for 1 h.
  7. Rinse a second, larger ultrasonic cleaner (UC2) with DI water and fill three-quarters of its volume with DI water.
  8. Turn off UC1 and remove the stainless steel rack. Immediately begin rinsing substrates with DI water over a sink.
    NOTE: Do not let the substrates dry at this stage.
  9. Transfer the stainless-steel rack to UC2 and fill completely with DI water such that the substrates are completely covered. Turn on UC2 to 40 kHz ultrasonic frequency and 600 W power and let the substrates sit for 30 min.
  10. Prepare the homemade IPA vapor dryer.
    1. Ensuring the valve is closed, hook up a gas hose to ultra-high purity (UHP) nitrogen. Open the nitrogen tank and set the regulator to 10 psi. Open the valve to nitrogen flow and adjust to 100 PSIG on the attached flow meter, then close the valve again.
    2. Fill a flask with 150 mL of fresh IPA and tightly cork the flask. The cork tightly seals the flask opening while allowing nitrogen and IPA to pass through two small metal pipe systems embedded in the cork. These connect to a small metal piping system with fine holes, which sits above UC2 such that nitrogen/IPA vapor is incident on the substrates.
  11. When the UC2 rinse cycle is done, turn off the heat and UC2.
  12. Open the vapor dryer valve to the nitrogen and IPA and open the drain valve on UC2 such that the DI water comes out very slowly.
    NOTE: The DI water must be drained very slowly. This process replaces the DI water with nitrogen/IPA vapor to prevent water spots from forming on the substrates. This should take 1–2 h for 30,000 cm3 of water.
  13. When drained completely, remove the rack from UC2 and close the vapor dryer valve.
  14. Store in a clean and contained environment for future use.
    NOTE: Cleaned substrates can be left in this environment indefinitely, as long as they remain clean. Inspect cleaned substrates before further use to ensure they do not need to undergo the cleaning process again.

2. Magnesium zinc oxide window layer sputter deposition

NOTE: This MgZnO sputter-deposition process utilizes an unbalanced magnetron and a 4" diameter, 0.25" thick target with a target-to-substrate distance of 15 cm. The target is 99.99% purity (MgO)11(ZnO)89 by percent weight.

  1. Sputter system start-up
    1. Switch on the mechanical pump and foreline valve, followed by the diffusion pump for the sputter chamber. Ensure that the target cooling water is on and that the mechanical valves to the target cooling water are open.
    2. Turn on the load lock pump using the switch on the pump.
    3. Let the diffusion pump warm up for 15 min.
    4. Check the chamber pressure on the pressure gauge: if it is below 2.0 x 10-1 Torr, open the diffusion pump gate valve. If the pressure is greater than 2.0 x 10-1 Torr, switch the foreline valve to close, and open the roughing valve until the pressure drops. Then, switch closed the roughing valve, open the foreline, and manually open the diffusion pump gate valve.
    5. In the computer software, set the run pressure to 5 mTorr and click "gas enable", which enables the gas flow. The flow should be ~19–20 sccm and oxygen set to 3% of the total flow with the balance as argon in the software.
    6. Allow the chamber to pump for 10 min.
    7. Check that the base pressure is below 1.0 x 10-5 Torr on the ion gauge readout.
    8. Ensure that the transfer arm is fully retracted from the chamber (look through the chamber viewport to ensure the sample holder is not in the chamber), and switch the load lock gate valve closed.
    9. Ensure that the shutter is closed: this can be checked by looking through the viewport window to see that it is directly above the sputter cathode.
    10. On the power supply, set the RF generator power to 60 W. In the computer software increase the pressure to 15 mTorr for plasma ignition, turn the RF power on, and once the plasma has ignited, reduce the pressure back to 5 mTorr in the software. The reflected power should be 1–2 W. If it is much higher, the RF match network must be tuned.
    11. The target must be warmed up to avoid cracking: increase the power on the RF power generator at a rate of 20 W/min until reaching a final power of 140 W. The reflected power should ideally be <5% of the real power. Allow the target to pre-sputter with the shutter closed for 15 min.
  2. MgZnO sputter deposition
    1. To calibrate the deposition rate, a witness sample must be fabricated. Use a permanent marker to draw a ~0.2 cm (length) line on the TCO-coated side of a clean substrate.
    2. Ensure that the load lock gate valve is closed, then loosen and open the load lock door knob. Vent the load lock with a quarter-turn of the UHP nitrogen vent valve until the load lock door loosens. Keep the vent valve partially open to purge the load lock while the door is open.
    3. Use a handheld air blower to gently remove any dust particles from the clean TCO-coated substrate. Remove any substrate on the sample holder and load the clean substrate TCO side-down using a pair of rubber-tipped tweezers. Hold the sample on the edge to avoid the deposition area.
    4. Close and tighten the load lock door. Switch on the load lock pump and close the nitrogen vent valve.
    5. Pump the load lock down until the load lock pressure gauge reads below 5.0 x 10-2 Torr. Then switch off the load lock pump and switch open the load lock gate (the pressure should not spike above 7 mTorr). Wait for the pressure to level and manually insert the transfer arm such that the sample sits above the shuttered cathode.
    6. Set the desired deposition time on a timer and begin timing as the shutter is being manually opened. Immediately close the shutter as the timer goes off.
    7. Manually retract the transfer arm completely and close the load lock gate.
    8. Remove or exchange the sample following steps 2.2.2–2.2.5.
    9. To obtain the MgZnO deposition rate, remove the permanent marker from the witness sample with a cotton-tipped applicator dipped in methanol. Measure the thickness using a profilometer17 and set subsequent deposition times for the desired MgZnO thickness (100 nm for the samples presented in this work).
    10. Repeat the deposition for as many samples as is desired.
      NOTE: After MgZnO deposition, the samples can be stored for some time. At the risk of oxidizing, it is recommended they be stored in a desiccator under vacuum for no more than 1 week for best results.

3. Close-space sublimation deposition and treatment of absorber layers

  1. CSS system start-up
    1. Ensure that 1) the system is under vacuum, 2) the mechanical and diffusion pumps are on, 3) the load lock gate valve is open to the chamber, and 4) the pressure is set to 40 mTorr.
    2. Manually open the gas flow valve (98% N2 and 2% O2) and select "Gas enable" on the computer software. The pressure should stabilize around 40 mTorr.
    3. Turn on the residual gas analyzer (RGA) by opening the RGA valve and connecting to the software program. This is necessary to track water, oxygen, nitrogen, and hydrogen levels in the system. These levels are typically around 4.5 x 10-9, 2.5 x 10-8, 2.3 x 10-6, and 8.0 x 10-10 Torr for each, respectively.
    4. Bring the CSS system top and bottom sources up to operating temperatures in the computer program. Top source temperatures are set to 620 °C for preheat, 360 °C for CdTe, 420 °C for CdSe20Te80, 387 °C for CdCl2, 400 °C for anneal, and 620 °C for bakeoff. Bottom source temperatures are set to 620 °C for preheat, 555 °C for CdTe, 545 °C for CdSe20Te80, 439 °C for CdCl2, 400 °C for anneal, and 620 °C for bakeoff. These temperature differentials promote sublimation from the bottom to top sources such that material sublimates onto the sample, located in between the sources.
    5. When the sources have reached operating temperatures, run the sample holder through the bakeoff recipe: in the software, select "Bakeoff" in the recipe list and click "Run". This will automatically move the transfer arm such that the sample holder stays in the bakeoff source for 480 s. This heats up the sample holder and bakes off any excess material.
    6. After the transfer arm automatically retracts the sample holder to the home position and closes the gate valve, vent the load lock by opening the UHP nitrogen vent valve. When vented, open the load lock door and close the vent valve.
  2. CSS deposition and passivation treatment of absorbers
    1. Use a handheld air blower to gently remove any dust particles from the clean MgZnO/TCO-coated substrate and load the substrate onto the sample holder (MgZnO side down).
    2. Close the load lock door and pump down the load lock by turning on the load lock roughing switch.
    3. While pumping down, input the desired recipe for CSS deposition into the computer program. The recipes used to prepare the CdTe and CdSeTe/CdTe structures are different at this stage and are as follows.
    4. For the CdTe witness sample (for determination of CdTe deposition rate; required for both CdTe and CdSeTe/CdTe device fabrication), use:
      110 s in preheat source (this raises the glass to ~480 °C such that CdTe will properly sublimate onto the substrate);
      110 s in CdTe source (this sublimates CdTe onto the substrate);
      180 s in CdCl2 source [the CdCl2 deposition is necessary for good CdTe device performance (it has been shown that it passivates grain boundaries and dangling bonds and promotes grain growth and alignment in the polycrystalline CdTe absorber12,13,14,15,16)];
      240 s in anneal source (this drives the CdCl2 into the absorber material); and
      300 s in cooling source (this allows the sample to cool for unloading).
    5. Using a razor blade, scribe a small area of CdTe material off the substrate and measure the CdTe film thickness using a surface profilometer to determine deposition rate17.
    6. For the CdSeTe witness sample (for determination of CdSeTe deposition rate; required only for CdSeTe/CdTe device fabrication), use:
      140 s in preheat source (this raises the glass to ~540 °C such that CdSeTe will properly sublimate onto the substrate);
      300 s in CdSeTe source (this sublimates CdSeTe onto the substrate); and
      300 s in cooling source.
    7. Using a razor blade, scribe a small area of CdSeTe material off the substrate and measure the CdSeTe film thickness using a surface profilometer to determine deposition rate17.
    8. For the thin single absorber (CdTe sample), use:
      110 s in preheat source;
      xx s in CdTe source [the dwell time depends on the CdTe deposition rate and desired thickness (for the 1.5 μm single CdTe absorber used here, the dwell time is 60 s)];
      150 s in CdCl2 source [the CdCl2 treatment is dependent on absorber thickness; therefore, experiments should be conducted to optimize the treatment conditions (the listed dwell times are optimized for thin, 1.5 μm absorbers18)];
      240 s in anneal source; and
      300 s in cooling source.
    9. For the thin bilayer absorber (CdSeTe/CdTe sample), use:
      140 s in preheat source;
      xx s in CdSeTe source [again, the dwell time depends on the CdSeTe deposition rate and desired thickness (for the 0.5 μm CdSeTe layer used here, the dwell time is 231 s)];
      xx s in CdTe source [the dwell time depends on the desired CdTe thickness and deposition rate calculated from the measured thickness of the CdTe witness sample (for the 1.5 μm bilayer CdSeTe/CdTe absorber used here, the dwell time is 50 s for a 1.0 μm CdTe layer)];
      150 s in CdCl2 source;
      240 s in anneal source; and
      300 s in cooling source.
    10. When the load lock pressure reads below 40 mTorr in the computer software, using the software, open the load lock gate valve and select "Start". The program automatically runs the selected recipe and will return to the home position upon completing the cooling step10.
    11. After the full deposition is complete open the load lock vent valve, vent to atmosphere, and open the load lock door for final substrate cooling. After ~60 s, the substrate should be cool enough to remove from the sample holder with a lint-free cloth.
    12. Once the sample is removed, close the load lock door, pump down the load lock by turning on the roughing switch, and follow step 3.1.5 to run the bakeoff recipe. A bakeoff must be run between each sample deposition to clean the sample holder.
    13. The processed sample should have a white hazy layer on the film from the CdCl2 treatment. Take a picture of the film to note the haze pattern. If there is little or no visible material from the CdCl2 treatment, this treatment likely needs optimization.
    14. Rinse the excess CdCl2 material off of the film into a graduated beaker using DI water and dry the film with compressed argon.
      CAUTION: This CdCl2 rinse should be performed in a contained enclosure. Upon completion, dispose of the CdCl2/DI water mixture in the proper hazardous waste container.
      NOTE: After CSS deposition, the samples can be stored for some time, but it is recommended they be stored in a desiccator under vacuum for no more than 1 week for best results. A schematic of the automated in-line CSS deposition system is shown in Figure 2.

4. Close-space sublimation copper treatment

  1. CSS system start-up
    1. Ensure that the mechanical and diffusion pumps are on.
    2. Open the process gas valve and manually adjust the gas flow control knob until the 40 mTorr operating pressure is displayed on the pressure gauge.
    3. Manually set and turn on the CSS sources using proportional-integral-derivative (PID) controllers. The top source temperatures used in this experiment are 330 °C for the preheat source, 170 °C for the CuCl source, and 200 °C for the anneal source. The bottom source temperatures are 330 °C for the preheat source, 190 °C for the CuCl source, and 200 °C for the anneal source.
    4. Switch open the diffusion pump valve and manually close the load lock gate valve.
  2. CuCl treatment on absorber structures
    1. When the sources have reached operating temperature, the sample can be loaded onto the sample holder:
      1. Loosen the knob for the load lock door.
      2. Vent the load lock with a quarter turn of the UHP nitrogen vent valve.
      3. Open the load lock door and use a handheld air blower to gently remove any dust particles from the sample. Place the sample film side down onto the sample holder using a pair of rubber-tipped tweezers, holding the sample on the edge to avoid the deposition area.
      4. Close the vent valve and close and tighten the load lock door.
      5. Manually open the load lock pump and let the load lock pump below the crossover pressure (40 mTorr).
    2. When the crossover pressure is obtained, manually close the load lock pump and manually open the load lock gate valve.
    3. Manually move the transfer arm into the preheat, CuCl, and anneal positions sequentially. A timer is used for the dwell time in each position. For the samples described, the dwell times are 75 s, 5 s, and 250 s for the preheat, CuCl, and anneal sources, respectively.
    4. After the annealing step, manually bring the transfer arm back to the home position and close the load lock gate valve.
    5. Follow step 4.2.1 to exchange samples.
      NOTE: When unloading a previous sample, it is still likely hot. Remove the sample with a pair of rubber-tipped tweezers and let it cool (film side up) on a metal block. After the Cu treatment, the samples can be stored for some time, but it is recommended they be stored in a desiccator under vacuum for no more than 1 week for best results.

5. Evaporation deposition of thin tellurium

  1. Turn on the mechanical pump, foreline valve, and diffusion pump using switches on the evaporator system. Allow the diffusion pump to warm up for 20 min.
  2. Vent and open the chamber by opening the nitrogen vent valve and lifting the evaporator chamber. Load the Te into the alumina-coated molybdenum boat. Move the evaporator chamber back into place after the material is loaded.
  3. Enter the proper settings for Te deposition from an alumina-coated molybdenum boat in the quartz crystal monitor (QCM) panel (density = 6.25 g/cm3 and acoustic impedance = 9.81 g/cm2s).
  4. Open the chamber top to access the sample holder. Use a handheld air blower to gently remove any dust particles from the sample. Load the sample film side down onto the sample holder and close the chamber top.
  5. Manually move the lever into the roughing position; both the roughing and chamber pressure readouts should begin to drop. Allow the pressure to drop below 10 mTorr.
  6. Turn the foreline valve back to the foreline position. Wait ~30 s for any momentary spike in pressure to be resolved, then open the high vacuum valve. When the chamber pressure reader has based out, the proper deposition pressure of 1.0 x 10-5 Torr has been reached.
  7. Turn on the power switch, open the shutter, and turn up the current control to begin deposition. The optimal current operating range is 90–100 AC amperes such that the deposition rate will be ~5–10 Å/s. The deposition rate, displayed on the QCM readout, can change rapidly; therefore, the current must be continuously adjusted during the deposition to maintain the rate between 5–10 Å/s.
  8. When the QCM displays the desired Te thickness (40 nm for the samples used here), quickly and concurrently turn the current to zero, turn off the power switch, and close the shutter.
  9. Close the high vacuum valve, open the nitrogen vent valve, and remove the sample from the sample holder. Repeat steps 5.4–5.8 for deposition on additional samples.
    NOTE: After the Te deposition, the samples can be stored for some time, but it is recommended they be stored in a desiccator under vacuum for no more than 1 week for best results.

6. Nickel back contact application

CAUTION: Due to the fumes from the Ni paint and methyl ethyl ketone (MEK), always run an overhead fan to cycle air during this process.

  1. Mount the samples (film side facing forward) onto a vertical mounting shelf.
  2. Ensure that the Ni applicator gun is clean throughout. If not, clean with MEK.
  3. The back contact is a mixture of conductive Ni paint and thinner at a 2:1 ratio. Before applying the paint, shake the back-contact solution to ensure complete mixing.
  4. Pour the Ni back contact solution into the applicator gun and turn on the attached air compressor hose. Spray a test piece (i.e., cardboard) to ensure that the paint applies uniformly. If it is uniform, apply the back contact to the samples by spraying the solution across the sample set with a slow lateral motion. Allow the back contact to dry slightly and apply as many times as is needed for complete coverage (typically, five passes works well).
    NOTE: The Ni solution can dry and clog the applicator gun; therefore, to avoid a de-clogging process during back-contact application, it is important to wait no more than 60 s between spray sets.
  5. Turn off the air compressor and allow the back contact to dry on the samples for at least 1 h.

7. Delineation into 25 small-area devices

NOTE: To finish the thin film structure into electrically contact-able devices, the film stack must be delineated into small area devices such that the TCO front contact and Ni back contact are electrically accessible. This is done using a metal mask with mechanical removal of the semiconductor.

  1. Place a sample into the metal mask.
  2. Place the masked sample in the glovebox and using a siphon hose, apply the glass, beaded media to the unmasked portions of the sample. Proper material removal is achieved when the mask windows become almost transparent.
  3. Repeat this process with the second mask such that upon completing delineation, 25 small area square devices appear in a 5 x 5 pattern on the sample. The completed areas are ~0.6 cm2.
  4. Clean the film side of the samples with a cotton-tipped applicator dipped in DI water.
  5. To minimize lateral resistance in electrical measurements of the finished devices, solder a grid pattern between the devices with an indium solder.
    NOTE: The completed device structures are given in Figure 1A and Figure 1B for the CdTe and CdSeTe/CdTe absorber devices, respectively.

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Representative Results

The addition of CdSeTe to a thin CdTe absorber improves device efficiency through superior absorber material quality and higher short-circuit current density (JSC). Figure 3A and Figure 3B, (adapted from Bothwell et al.8) show PL and TRPL, respectively, for the single CdTe absorber and CdSeTe/CdTe bilayer absorber devices. Both PL and TRPL measurements clearly show improved photoluminescence with the CdSeTe/CdTe bilayer absorber. The PL intensity improves by a factor of six, and the TRPL tail lifetime, fit with a single exponential to the slow part of the decay, is 12.6 ± 0.1 ns for the bilayer structure (compared to 1.6 ± 0.02 ns for the monolayer structure), which indicates better CdSeTe material quality. The PL measurement also verifies the successful incorporation of the CdSeTe layer. The shift in peak PL intensity, which corresponds to absorber band gap, from 1.50 to 1.42 eV, confirms that the lower band gap CdSeTe material is operative in the absorber layer.

Higher JSC in the bilayer absorber is demonstrated by current density-voltage (J-V) and quantum efficiency (QE) measurements, shown in Figure 4 and Figure 5, respectively. The shift in the light J-V curves along the current density axis shown in Figure 4 corresponds to a change in JSC from 24.0 mA/cm2 to 25.5 mA/cm2 for the best-performing CdTe and CdSeTe/CdTe devices respectively.

QE measurements of the CdTe and CdSeTe/CdTe devices (Figure 5A and Figure 5B, respectively) show the bilayer device’s additional photon conversion in the long wavelength range and corroborate the increase in JSC for that device. JSC values, determined by integrating the QE data over the wavelength range19 are 24.6 mA/cm2 for the CdTe device and 25.9 mA/cm2 for the CdSeTe/CdTe device. Employing optical transmission data measured on a 0.5 μm CdSeTe film, the QE data for the bilayer device is separated into current collected in the CdSeTe and CdTe layers8. This highlights the dominant role the CdSeTe plays in absorption. The current density collected in the CdSeTe layer is 22.9 mA/cm2 compared to 3.0 mA/cm2 in the CdTe layer, such that CdSeTe accounts for ~90% of the current collection in the bilayer absorber.

The effectiveness of a bilayer absorber depends on optimization of the fabrication process. Illuminated J-V data in Figure 6 demonstrate the importance of optimizing the CdSeTe:CdTe thickness ratio: the data show a significant kink in the non-optimal 1.25-µm CdSeTe/0.25-µm CdTe device. The kink, likely due to back barrier effects, generates a notable decrease in device efficiency to 11.0%. Optimized CdCl2 passivation is also vital to good device performance. Thin CdTe devices demonstrate sensitive dependence on CdCl2 deposition time18, and with no CdCl2 passivation, device efficiencies can fall to ~2%11. Although the authors have found CdCl2 passivation and the CdSeTe:CdTe thickness ratio to be among the most significant process conditions, optimization of all fabrication stages and parameters is necessary.

Figure 1
Figure 1: Device structure of completed CdTe-based photovoltaic devices. (A) A 1.5 μm CdTe absorber device structure was used as a reference for comparison with the bilayer structure. (B) A 0.5 μm CdSeTe/1.0 μm CdTe device structure was fabricated to improve photovoltaic efficiency. Please click here to view a larger version of this figure.

Figure 2
Figure 2: Automated in-line vacuum close-space sublimation deposition system. Shown is a 2D schematic providing configuration details of the sample holder, load lock, vacuum enclosure, and individual sources. Please click here to view a larger version of this figure.

Figure 3
Figure 3: Photoluminescence comparison of CdTe and CdSeTe/CdTe devices. (A) Peak PL intensity increases 6-fold with the incorporation of CdSeTe, and peak position shifts to a lower band gap, indicating the successful incorporation of CdSeTe. (B) TRPL tail lifetime, fit with a single exponential to the slow part of the decay, is notably longer for the CdSeTe/CdTe device than the CdTe device, which indicates better material properties of the CdSeTe layer. This figure is reprinted from Bothwell et al.8 Please click here to view a larger version of this figure.

Figure 4
Figure 4: J-V comparison of CdTe and CdSeTe/CdTe devices. J-V data under illumination show an increase in JSC, measured at the zero-voltage point, from 24.0 mA/cm2 to 25.5 mA/cm2 for the CdTe and CdSeTe/CdTe devices, respectively. Dark J-V data are also shown for comparison. Please click here to view a larger version of this figure.

Figure 5
Figure 5: QE comparison of CdTe and CdSeTe/CdTe devices. The (A) QE data of the CdTe device and (B) CdSeTe/CdTe device show an increase in JSC from 24.6 mA/cm2 to 25.9 mA/cm2, as determined by integrating the QE data over the wavelength range. Transmission measurements on a 0.5 μm CdSeTe film were used to separate the QE signal in (B) into current collected in the CdTe and CdSeTe layers: the CdSeTe layer constitutes ~90% of current collection in the 1.5 μm bilayer device. Please click here to view a larger version of this figure.

Figure 6
Figure 6: J-V comparison of optimized and non-optimized CdSeTe/CdTe devices. J-V data under illumination of a CdSeTe/CdTe device with a non-optimized CdSeTe:CdTe thickness ratio show a kink in the curve and reduction in the device efficiency, which emphasizes the importance of optimizing the CdSeTe:CdTe thickness ratio. Dark J-V data are also shown for comparison. Please click here to view a larger version of this figure.

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Discussion

Thin bilayer CdSeTe/CdTe photovoltaic devices demonstrate improvements in efficiency compared to their CdTe counterparts because of better material quality and increased current collection. Such enhanced efficiencies have been demonstrated in bilayer absorbers greater than 3 μm5,7, and now with optimized fabrication conditions, it has been demonstrated that increased efficiencies are also achievable for thinner, 1.5-μm bilayer absorbers.

The optimization of the fabrication process for thin bilayer absorbers is rooted in three main modifications: substrate preheat temperature, CdSeTe:CdTe thickness ratio, and CdCl2 passivation. For proper CdSeTe sublimation, the preheat temperature of the substrate should be ~540 °C compared to ~480 °C for CdTe sublimation, which is accomplished by varying the substrate dwell time in the preheat source. To prevent contact barriers in the device while maintaining good open circuit voltage (VOC), it was found that 0.5 μm CdSeTe/1.0 μm CdTe is the optimal ratio in the thin bilayer devices, as demonstrated in Figure 6. CdCl2 treatment of the bilayer absorber, essential for passivation of grain boundaries and promotion of grain growth and alignment12,13,14,15,16, can be especially sensitive in thin absorbers18. It was determined that a much less aggressive CdCl2 treatment, involving both source temperatures and dwell times, was needed to properly passivate the thin bilayer absorbers18 compared to thick bilayer absorbers5.

The CSS automated in-line vacuum system and multi-layer, multi-step fabrication process provides the opportunity for modifications throughout the device structure. The CdSeTe layer, sublimation-deposited from the CdSe20Te80 source in this study, can also be deposited by co-sublimation from CdSe and CdTe sources. Some initial work has been conducted at Colorado State University involving co-sublimation deposition of CdSeTe with limited success20. The CdSeTe/CdTe interface can also be adjusted by controlling the interdiffusion of the CdSeTe and CdTe layers.

There is no purposeful interdiffusion in the thin bilayer devices presented; however, interdiffusion of the layers is promoted in thicker bilayers and is accomplished by increasing the anneal time after CdCl2 deposition for a thermally driven interdiffusion process5. Control of the extent of interdiffusion allows for some band gap engineering of the bilayer absorber and can be used to adjust photon absorption profiles and current collection in completed devices. Different dopants, such as group-V dopants6,21,22, can also be incorporated to replace the historically used Cu dopant. Group-V doping offers higher achievable absorber doping levels of 1.0E17 cm-3, demonstrates long-term stability6, and can be incorporated seamlessly into the CSS-deposition process by using a doped source material for sublimation (currently being explored by colleagues at Colorado State University)23,24. Additional layers in the thin-film structure can also be modified in large or small ways if desired. Options include complete material removal or replacement, fabrication method changes, or variations in deposition conditions or post deposition treatments.

One bilayer property that makes the CdSeTe/CdTe absorber favorable compared to a CdTe absorber also serves as a limitation. The lower, 1.42 eV band gap of the bilayer absorber vs. the 1.50 eV band gap of the monolayer CdTe absorber increases photon collection for enhanced JSC, but the lower band gap also inherently limits the maximum achievable open-circuit voltage (VOC), thus limiting device efficiency. To mitigate this limitation, the next step in improving the thin CdSeTe/CdTe device structure is to incorporate a higher band gap material at the back of the device to increase VOC.

Modeling has demonstrated that the incorporation of a thin, ~100 nm, 1.8 eV material after the CdTe layer will create a conduction band barrier at the back and reduce back surface recombination by reflecting photoelectrons and forward current electrons away from the recombination-prone back surface25,26. This “electron reflector” structure requires a fully-depleted absorber such that the absorber thickness is limited to less than 2 μm25, making the thin bilayer absorber well-suited for this configuration. Cadmium magnesium telluride (CdMgTe), a high band gap CdTe alloy material, is an ideal candidate for this layer because of its tunable band gap and straightforward incorporation into the existing device fabrication process by co-sublimation or sputter deposition.

Increased device efficiency through enhanced current collection and photoluminescent properties of thin CdSeTe/CdTe bilayer devices is significant for fabrication time and cost reduction, and future improvements to the device structure and VOC. The CSS automated in-line vacuum system used for absorber deposition and passivation in this study is noteworthy for its deposition speed. Other fabrication methods such as sputtering and metal organic chemical vapor deposition (MOCVD) can take more than fifteen times as long for the same deposition27,28.

In-line CSS also offers scalability options. The fabrication processes used to make the small area research devices presented can be implemented in larger scale processes for PV module fabrication with minimal loss in fabrication parameterization. The CdSeTe/CdTe bilayer structure presented in this work also bears significance with its success using the very thin absorber. Specifically, device efficiency nearing 16% with only a 1.5-μm bilayer absorber demonstrates the benefit of CdSeTe to CdTe even in ultra-thin absorbers. Thin absorber layers such as these offer further fabrication time and material savings, and the opportunity to explore an electron reflector structure to minimize the voltage deficit present in CdSeTe/CdTe devices.

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Disclosures

The authors have nothing to disclose.

Acknowledgments

The authors would like to thank Professor W.S. Sampath for use of his deposition systems, Kevan Cameron for system support, Dr. Amit Munshi for his work with thicker bilayer cells and supplemental footage of the in-line automated CSS vacuum deposition system, and Dr. Darius Kuciauskas for assistance with TRPL measurements. This material is based upon work supported by the U.S. Department of Energy’s Office of Energy Efficiency and Renewable Energy (EERE) under Solar Energy Technologies Office (SETO) Agreement Number DE-EE0007543.

Materials

Name Company Catalog Number Comments
Alpha Step Surface Profilometer Tencor Instruments 10-00020 Instrument for measuring film thickness
CdCl2 Material 5N Plus N/A Material for absorber passivation treatment
CdSeTe Semiconductor Material 5N Plus N/A P-type semiconductor material for absorber layer
CdTe Semiconductor Material 5N Plus N/A P-type semiconductor material for absorber layer
CESAR RF Power Generator Advanced Energy 61300050 Power generator for MgZnO sputter deposition
CuCl Material Sigma Aldrich N/A Material for absorber doping
Delineation Material Kramer Industries Inc. Melamine Type 3 60-80 mesh Plastic beading material for film delineation
Glovebox Enclosure Vaniman Manufacturing Co. Problast 3 Glovebox enclosure for film delineation
Gold Crystal Kurt J. Lesker Company KJLCRYSTAL6-G10 Crystal for Te evaporation thickness monitor
HVLP and Standard Gravity Feed Spray Gun Kit Husky HDK00600SG Applicator spray gun for Ni paint back contact application
MgZnO Sputter Target Plasmaterials, Inc. PLA285287489 N-type emitter layer material
Micro 90 Glass Cleaning Solution Cole-Parmer EW-18100-05 Solution for initial glass cleaning
NSG Tec10 Substrates Pilkington N/A Transparent-conducting oxide glass for front electrical contact
Super Shield Ni Conductive Coating MG Chemicals 841AR-3.78L Conductive paint for back contact layer
Te Material Sigma Aldrich MKBZ5843V Material for back contact layer
Thickness Monitor R.D. Mathis Company TM-100 Instrument for programming and monitoring Te evaporation conditions
Thinner 1 MG Chemicals 4351-1L Paint thinner to mix with Ni for back contact layer
Ultrasonic Cleaner 1 L & R Electronics Q28OH Ultrasonic cleaner 1 for glass cleaning
Ultrasonic Cleaner 2 Ultrasonic Clean 100S Ultrasonic cleaner 2 for glass cleaning
UV/VIS Lambda 2 Spectrometer PerkinElmer 166351 Spectrometer used for transmission measurements on CdSeTe films

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References

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