Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

Summary

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

Abstract

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and entanglement, to solve certain problems exponentially faster than with the best known algorithms on a classical computer. Gate-defined lateral quantum dots on GaAs/AlGaAs are one of many avenues explored for the implementation of a qubit. When properly fabricated, such a device is able to trap a small number of electrons in a certain region of space. The spin states of these electrons can then be used to implement the logical 0 and 1 of the quantum bit. Given the nanometer scale of these quantum dots, cleanroom facilities offering specialized equipment- such as scanning electron microscopes and e-beam evaporators- are required for their fabrication. Great care must be taken throughout the fabrication process to maintain cleanliness of the sample surface and to avoid damaging the fragile gates of the structure. This paper presents the detailed fabrication protocol of gate-defined lateral quantum dots from the wafer to a working device. Characterization methods and representative results are also briefly discussed. Although this paper concentrates on double quantum dots, the fabrication process remains the same for single or triple dots or even arrays of quantum dots. Moreover, the protocol can be adapted to fabricate lateral quantum dots on other substrates, such as Si/SiGe.

Introduction

Quantum information science has drawn a lot of attention ever since it was shown that quantum algorithms can be used to solve certain problems exponentially faster than with the best known classical algorithms¹. An obvious candidate for a quantum bit (qubit) is the spin of single electron confined in a quantum dot since it is a two-level system. Numerous architectures have been suggested for the implementation of quantum dots, including semiconducting nanowires², carbon nanotubes³, self-assembled quantum dots⁴, and semiconductor vertical⁵ and lateral quantum dots⁶. Gate-defined lateral quantum dots in G....

Protocol

The fabrication process described below is done on a GaAs/AlGaAs substrate with dimensions of 1.04 x 1.04 cm. Twenty identical devices are fabricated on a substrate of this size. All steps of the process are done in a cleanroom and appropriate protective gear must be used at all times. Deionized water is used throughout the process, but is simply referred to as "water" in the protocol below.

1. Etching of the Mesa

The result of this fabrication step is shown in Figure 4a.

1. Place the sample in a plasma asher with an O₂ plasma at 75 W for 2 min to remove any t....

Results

One of the critical steps in the process described above is the etching of the mesa (step 1). It is important to etch enough to remove the 2DEG below while avoiding overetching. Therefore, it is recommended to use a bulk GaAs dummy sample to test the etching solution before performing the etch on the GaAs/AlGaAs sample. The etch rate of the GaAs/AlGaAs heterostructure is larger than that of GaAs, but the etching of the dummy can give an indication to whether the solution is more or less reactive than usual and the etch t.......

Discussion

The process presented above describes the fabrication protocol of a double quantum dot able to reach the few-electron regime. However, the parameters given may vary depending on the model and calibration of the equipment used. Therefore, parameters such as the doses for exposures during the e-beam and photolithography steps will have to be calibrated before the fabrication of devices. The process can easily be adapted to the fabrication of gate-defined quantum dots on other types of substrates, such as Si/SiGe, that also.......

Materials

List of materials used in this article

Name	Company	Catalog Number	Comments
Acetone - CH3COCH3	Anachemia	AC-0150	67-64-1
Isopropyl Alcohol (IPA) - (CH3)2CHOH	Anachemia	AC-7830	67-63-0
1165 Remover	MicroChem Corp	G050200	872-50-4
Microposit MF-319 Developer	Shipley	38460	75-59-2
Sulfuric Acid - H2SO4	Anachemia	AC-8750	766-93-9
Hydrogen Peroxide (30%) - H2O2	Fisher Scientific		7722-84-1
LOR 5A Lift-off resist	MicroChem Corp	G516608	120-92-3
Microposit S1813 Photo Resist	Shipley	41280	108-65-6
Microposit S1818 Photo Resist	Shipley	41340	108-65-6
PMMA LMW 4% in anisole	MicroChem Corp		100-66-3, 9011-14-7
PMMA HMW 2% in anisole	MicroChem Corp		100-66-3, 9011-14-7
GaAs/AlGaAs wafer	National Research Council Canada	See detailed layer structure in Figure 1.
Ni (99.0%)	Anachemia
Ge (99.999%)	CERAC inc.
Au (99.999%)	Kamis inc.
Ti (99.995%)	Kurt J Lesker
Al	Kamis inc.
Silver Epoxy	Epoxy Technology	H20E