Scanning-probe Single-electron Capacitance Spectroscopy

Summary

Scanning-probe single-electron capacitance spectroscopy facilitates the study of single-electron motion in localized subsurface regions. A sensitive charge-detection circuit is incorporated into a cryogenic scanning probe microscope to investigate small systems of dopant atoms beneath the surface of semiconductor samples.

Abstract

The integration of low-temperature scanning-probe techniques and single-electron capacitance spectroscopy represents a powerful tool to study the electronic quantum structure of small systems - including individual atomic dopants in semiconductors. Here we present a capacitance-based method, known as Subsurface Charge Accumulation (SCA) imaging, which is capable of resolving single-electron charging while achieving sufficient spatial resolution to image individual atomic dopants. The use of a capacitance technique enables observation of subsurface features, such as dopants buried many nanometers beneath the surface of a semiconductor material^1,2,3. In principle, this technique can be applied to any system to resolve electron motion below an insulating surface.

As in other electric-field-sensitive scanned-probe techniques⁴, the lateral spatial resolution of the measurement depends in part on the radius of curvature of the probe tip. Using tips with a small radius of curvature can enable spatial resolution of a few tens of nanometers. This fine spatial resolution allows investigations of small numbers (down to one) of subsurface dopants^1,2. The charge resolution depends greatly on the sensitivity of the charge detection circuitry; using high electron mobility transistors (HEMT) in such circuits at cryogenic temperatures enables a sensitivity of approximately 0.01 electrons/Hz^½ at 0.3 K ⁵.

Introduction

Subsurface Charge Accumulation (SCA) imaging is a low-temperature method capable of resolving single-electron charging events. When applied to the study of dopant atoms in semiconductors, the method can detect individual electrons entering donor or acceptor atoms, permitting characterization of the quantum structure of these minute systems. At its heart, SCA imaging is a local capacitance measurement⁶ well-suited for cryogenic operation. Because capacitance is based on electric field, it is a long-range effect that can resolve charging beneath insulating surfaces⁶. Cryogenic operation permits investigation of single-electron motion and quantum level spacing that would be unresolvable at room temperature^1,2. The technique can be applied to any system in which electron motion below an insulating surface is important, including the charging dynamics in two-dimensional electron systems at buried interfaces⁷; for brevity, the focus here will be on studies of semiconductor dopants.

At the most schematic level, this technique treats the scanned tip as one plate of a parallel-plate capacitor, although realistic analysis requires a more detailed description to account for the curvature of the tip^8,9. The other plate in this model is a nanoscale region of the underlying conducting layer, as shown in Figure 1. Essentially, as a charge enters a dopant in response to a periodic excitation voltage, it gets closer to the tip; this movement induces more image charge on the tip, which is detected with the sensor circuit⁵. Similarly, as the charge exits the dopant, the image charge on the tip is decreased. Hence the periodic charging signal in response to the excitation voltage is the detected signal - essentially it is capacitance; thus this measurement is often referred to as determining the C-V characteristics of the system.

During the capacitance measurement, the only net tunneling is between the underlying conductive layer and the dopant layer - charge never tunnels directly onto the tip. The lack of direct tunneling to or from the tip during the measurement is an important difference between this technique and the more familiar scanning tunneling microscopy, although much of the hardware for this system is essentially identical to that of a scanning tunneling microscope. It is also important to note that SCA imaging is not directly sensitive to static charges. For investigations of static charge distributions, scanning Kelvin probe microscopy or electrostatic force microscopy is appropriate. Additional cryogenic methods for examining local electronic behavior exist which also have good electronic and spatial resolution; for example, scanning single-electron transistor microscopy is another scanning probe method capable of detecting minute charging effects^4,10. SCA imaging was originally developed at MIT by Tessmer, Glicofridis, Ashoori, and co-workers⁷; moreover, the method described here can be considered as a scanning probe version of the Single-Electron Capacitance Spectroscopy method developed by Ashoori and co-workers¹¹. A key element of the measurement is an exquisitely sensitive charge-detection circuit^5,12 using high electron mobility transistors (HEMT); it can achieve a noise level as low as 0.01 electrons/Hz^½ at 0.3 K, the base temperature of the cryostat in Reference 5. Such a high sensitivity allows observation of single-electron charging in subsurface systems. This method is suited for the study of electron or hole dynamics of individual or small groups of dopants in semiconductors, with typical dopant areal densities on the order of 10¹⁵ m^-2 in a plane geometry². An example of a typical sample configuration for this type of experiment is shown in Figure 1. The dopant layer is typically positioned a few tens of nanometers beneath the surface; it is important to know the precise distances between the underlying conducting layer and the dopant layer and between the dopant layer and the sample surface. In contrast to tunneling, capacitance does not fall off exponentially but instead essentially decreases in inverse proportion to the distance. Hence, the dopant depth could in principle be even deeper than tens of nanometers beneath the surface, as long as some reasonable fraction of electric field lands on the tip. For all of the aforementioned cryogenic local probes of electronic behavior, including the technique described here, spatial resolution is limited by the geometric size of the tip and by the distance between the subsurface feature of interest and the scanning probe tip.

Protocol

1. Protocol

1. Initial setup of microscope and electronics.
   1. Begin with a cryogenic-capable scanning probe microscope with associated control electronics. The microscopes used for the research described here use inertial translation to "walk" the sample towards and away from the tip along ramps¹³ (made from a conducting material such as copper, brass, or stainless steel to enable them to transmit bias voltage to the sample) as part of a Besocke design STM¹⁴, schematically shown in Figure 2.
   2. In addition to the bias voltage and tunneling current coaxial wires, provide at least two other coaxial wires and a ground wire which extend from the electronics rack to near the tip area of the microscope in order to operate the cryogenic amplifier circuit for sensitive charge detection. Assemble the elements of the amplifier circuit, described in detail in References 5, 12, and 15, that are housed on the electronics rack; this is the portion of the circuit outside the shaded box in Figure 2. This part of the circuit will remain at room temperature throughout the experiment.
2. Assemble the mounting chip for the tip and HEMT circuit (shaded box in Figure 2); the HEMT circuit will be lowered to cryogenic temperature to obtain optimal energy resolution.
   1. Cleave a square chip sized approximately 1 cm x 1 cm from a GaAs wafer using a scribe; the sensor circuit and tip will be mounted on this chip. Deposit approximately 100 nm of gold atop a titanium sticking layer through a shadowmask onto the GaAs chip to form several gold pads, each sized approximately 1 mm x 1 mm, to which wires from the HEMT and biasing resistor will be bonded. The dimensions of the pads are not critical.
   2. Prepare a sharp STM tip by mechanically cutting an 80:20 Pt:Ir wire using diagonal cutters. The tip can also be prepared by chemical etching or another method or can be purchased commercially. Determine the radius of curvature of the tip via scanning electron microscopy; the radius of curvature should be on the order of the spatial resolution needed for the experiment.
   3. Epoxy a gold wire onto each of the gold pads using conductive epoxy capable of withstanding cryogenic temperatures; these wires will connect the elements of the circuit on the mounting chip to the coaxial wires on the microscope. Since the gold wires can be easily removed after the next step if they are not needed, epoxy a few redundant gold wires onto the pads. Epoxy the HEMT, the biasing resistor, and the STM tip onto the GaAs mounting chip. Cure the epoxy as indicated on its product information sheet. (See the table of materials below for details.)
   4. Using a wire bonder loaded with gold wire, bond the source, drain, and gate elements of the HEMT to separate gold pads on the GaAs chip. Bond temporary wires connecting the gate and source or drain pads to ensure the gate does not become charged with respect to the source-drain channel. Use a grounding strap for added safety while manipulating the HEMT; it is important to take precautions to avoid introducing stray static charges that could destroy the HEMT.
   5. Store the prepared mounting chip with the wires attached to the gate and to the source-drain channel of the HEMT electrically connected to each other to avoid shorting the HEMT. If the temporary wires mentioned in the previous step have been removed, gently twist the wires together. It is simplest to connect all the wires to one another.
3. Attach the mounting chip to the microscope.
   1. Ensure that the gate and source-drain channels are never floating; this is to prevent destructive shorts between the gate and source-drain channels of the HEMT. Ground the coaxial wires on the microscope to which the wires from the chip will be soldered.
   2. Affix the mounting chip atop the scanning piezotube, as shown in Figure 2.
   3. Solder the gold wires extending from the mounting chip to the pertinent coaxial wires using indium solder.
4. Check the integrity of the HEMT using a curve tracer connected to the coaxial wires at the electronics rack. Essentially, the curve tracer shows the source-drain current-voltage characteristics. The most common failure mode is a short between the HEMT gate and its source-drain channel, which results in source-drain characteristics which are insensitive to gate voltage.
5. Mount the sample. Walk into range with the microscope configured in STM mode to ensure that the sample will successfully approach the tip.
   1. Connect wire T to the preamplifier used for STM tunneling current measurements, and attach DC bias voltage V_DC to wire B. (All connections are made at the electronics rack.)
   2. Walk in until the sample and tip are in tunneling range. When in range, the scanning piezotube should remain extended slightly from its equilibrium position so that grounding the scanning piezotube will cause the tip to retract from its in-range extension. This verifies that the sample can successfully approach the tip. Walk out of range after doing this, to protect the tip during the next actions.
   3. Transfer the microscope from the laboratory benchtop to the dewar for eventual low-temperature operation. At this point, the testing phase is complete and the experimental phase can begin.
6. Pump out the microscope to a vacuum of a few microtorr. Cool the microscope to 4.2 K or below for optimum energy resolution, following the procedure outlined in the manual for the cryostat.
   1. After cooling the microscope to its base temperature, allow the microscope sufficient time to reach thermal equilibrium; since repeated, lengthy scans of the same area will be performed, it is important to minimize thermal drift. (Drift is a shift in the equilibrium position of the tip with respect to the sample.)
   2. Suspend the dewar to isolate the microscope as much as possible from vibrations due to mechanical coupling to the building and to vacuum pumps and other devices attached to the microscope and dewar. This can be done using a bungee cord suspension system, as in Reference 15, or by using air springs or a similar method.
7. After cooling the microscope and before attempting data collection, verify the integrity of the HEMT again using the curve tracer.
8. Scan the sample in tunneling (STM) mode.
   1. Walk into range. Locate a region of the sample surface which is free from debris and from substantial height or conductivity variations, and ensure the tip is stable.
   2. Correct for any tilt of the sample; this is especially important because capacitance scans will be performed with the feedback loop disabled, thus the tip could crash into the surface if the scanning plane is not parallel to the surface of the sample. In principle, one could use the capacitance signal with feedback to maintain a constant capacitance while scanning the tip; however, in practice, the signal is not sufficiently robust to prevent a crash if feedback is used.
   3. Observe any thermal drift so that it can be compensated for by repositioning the tip offset. Note the amount of extension of the tip while in range in tunneling mode, referred to in this protocol as the touch point.
9. Move to an unperturbed area of the sample, one which was not scanned in STM mode.
   1. Disable the feedback loop in the STM controller. Recall that when the feedback loop is disabled, manual motions of the tip could inadvertently cause a crash. Great care should therefore be taken while moving the tip.
   2. Retract the tip a few tens of nanometers from the touch point.
   3. Offset the lateral position of the tip to a nearby area of the sample which has not recently been scanned, to avoid any perturbations (such as charging of semiconductor dopant sites) the bias voltage required to enable tunneling through the semiconducting sample for STM scanning may have induced.
   4. Cautiously extend the tip toward the surface until the tip displacement from equilibrium extension is close in magnitude to the touch point.
10. Switch wiring configuration to capacitance mode.
    1. Ground all coaxial wires to protect the HEMT.
    2. Connect the coaxial wires to the relevant voltage sources and resistors and to the lock-in amplifier and the function generator, as shown in Figure 2.
    3. Turn on all voltage sources. To avoid shocking the HEMT, begin with voltage source outputs at 0 V.
    4. Unground the coaxial wires, remembering to keep the gate and the source-drain channel of the HEMT connected to each other as long as possible in order to protect the HEMT.
    5. Set the voltage source on the voltage divider resistor (wire D).
    6. Tune the HEMT to its most sensitive region by monitoring the voltage across wire L with a multimeter while adjusting V_tune. Reattach wire L to the lock-in amplifier afterwards.
    7. Increase V_tune until the in-phase signal on the lock-in amplifier increases and begins to plateau; record this value of V_tune, which is the voltage applied to the tip. This enables all charge from the measurement to go to the HEMT instead of leaking through wire L.
    8. Optimize the internal phase of the lock-in amplifier using its autophase ability and record the phase value.
    9. Wait for the HEMT to stabilize to ensure there are no significant thermal effects (this often takes up to two hours).
11. Balance the HEMT by adjusting the signal on the standard capacitor to ensure that only the signal of interest goes to the lock-in amplifier. Adjustments of the signal on the standard capacitor can be done either to the amplitude of V_balance or to the relative phase between V_balance and V_excitation. The HEMT is considered balanced when the in-phase signal on the lock-in amplifier is minimized at this step of the procedure.
12. Perform scanning charge accumulation imaging.
    1. Set the DC bias voltage V_DC on the sample.
    2. Extend the tip to within 1 nm of the surface, using the touch point as reference.
    3. Record the output of the lock-in amplifier using the data acquisition software; this is the signal of interest.
    4. Scan the sample. To obtain good resolution, the scans may need to be acquired at the rate of several hours per scan to allow sufficient signal averaging for each pixel and to prevent smearing of the signal across adjoining pixels of the image. Perform several scans over the same area, and average these scans together to improve the signal-to-noise ratio.
13. Perform capacitance (C-V) spectroscopy with the tip stationary above a subsurface feature of interest in the charge accumulation image acquired during the previous step.
    1. Ramp V_DC and record the output of the lock-in amplifier using the data acquisition software.
    2. Take several capacitance vs. voltage (C-V) curves in the same location, and average these curves together to improve the signal-to-noise ratio. Typically, a few curves are averaged together. While averaging curves improves the signal-to-noise ratio, because of the potential for drift during scans, only a handful of successive scans should be averaged together.
14. Return to tunneling (STM) mode.
    1. Retract the tip to its equilibrium extension and reconfigure the electronics for STM. Re-enable the feedback loop and record the present in-range extension of the tip (touch point).
    2. Scan the area in tunneling mode to look for features in the topography which may have generated artifacts in the capacitance imaging and capacitance spectroscopy.
15. Analyze and interpret data, following Reference 9 and the supporting information in Reference ¹.

Results

The chief indicator of a successful measurement is reproducibility, much as in other scanning probe methods. Repeated measurements are very important for this reason. For point capacitance spectroscopy, taking many measurements in succession at the same location helps to increase the signal-to-noise ratio and identify spurious signals.

Once a feature of interest has been identified within the charge accumulation image and capacitance spectroscopy has been performed, interpretation of the C-V d...

Discussion

A detailed explanation of the theoretical basis for this experimental method is given in References 8 and 9 and discussed with respect to the scenario of subsurface dopants in Reference 2; the overview presented here will therefore be brief and conceptual. The tip is treated as one plate of a capacitor, and the conducting layer underlying the sample comprises the other plate. If the DC voltage is applied such that electrons are pulled toward the tip, and if there is a dopant atom situated between the underlying conductin...

Materials

List of materials used in this article

Name	Company	Catalog Number	Comments
Equipment
Besocke-design STM	Custom		References 14 and 15
Control electronics for STM	RHK Technology	SPM 1000 Revision 7
Lock-in amplifier	Stanford Research Systems	SR830
Curve tracer	Tektronix	Type 576
Oscilloscope	Tektronix	TDS360
Multimeter	Tektronix	DMM912
Wire bonder	WEST·BOND	7476D	with K~1200D temperature controller
Soldering iron	MPJA	301-A
Cryostat	Oxford Instruments	Heliox
Material
Pt/Ir wire, 80:20	nanoScience Instruments	201100
GaAs wafer	axt	S-I	For the mounting chip
99.99% Au wire, 2 mil diameter	SPM		For the mounting chip
99.99% Au wire, 1 mil diameter	K&S		For wire bonding
Indium shot	Alfa Aesar	11026
Silver epoxy	Epo-Tek	EJ2189-LV	Any low-temperature-compatible conductive epoxy is acceptable
HEMT	Fujitsu	Low Noise HEMT