Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Summary

Theoretical calculation and experimental verification are proposed for a reduction of threading dislocation (TD) density in germanium epitaxial layers with semicylindrical voids on silicon. Calculations based on the interaction of TDs and surface via image force, TD measurements, and transmission electron microscope observations of TDs are presented.

Abstract

Reduction of threading dislocation density (TDD) in epitaxial germanium (Ge) on silicon (Si) has been one of the most important challenges for the realization of monolithically integrated photonics circuits. The present paper describes methods of theoretical calculation and experimental verification of a novel model for the reduction of TDD. The method of theoretical calculation describes the bending of threading dislocations (TDs) based on the interaction of TDs and non-planar growth surfaces of selective epitaxial growth (SEG) in terms of dislocation image force. The calculation reveals that the presence of voids on SiO₂ masks help to reduce TDD. Experimental verification is described by germanium (Ge) SEG, using an ultra-high vacuum chemical vapor deposition method and TD observations of the grown Ge via etching and cross-sectional transmission electron microscope (TEM). It is strongly suggested that the TDD reduction would be due to the presence of semicylindrical voids over the SiO₂ SEG masks and growth temperature. For experimental verification, epitaxial Ge layers with semicylindrical voids are formed as the result of SEG of Ge layers and their coalescence. The experimentally obtained TDDs reproduce the calculated TDDs based on the theoretical model. Cross-sectional TEM observations reveal that both the termination and generation of TDs occur at semicylindrical voids. Plan-view TEM observations reveal a unique behavior of TDs in Ge with semicylindrical voids (i.e., TDs are bent to be parallel to the SEG masks and the Si substrate).

Introduction

Epitaxial Ge on Si has attracted substantial interests as an active photonic device platform since Ge can detect/emit light in the optical communication range (1.3-1.6 µm) and is compatible with Si CMOS (complementary metal oxide semiconductor) processing techniques. However, since the lattice mismatch between Ge and Si is as large as 4.2%, threading dislocations (TDs) are formed in Ge epitaxial layers on Si at a density of ~10⁹/cm². The performances of Ge photonic devices are deteriorated by TDs because TDs works as carrier generation centers in Ge photodetectors (PDs) and modulators (MODs), and as carrier recombination centers in laser dio....

Protocol

1. Theoretical calculation procedure

1. Calculate trajectories of TDs. In the calculation, assume the SEG masks to be thin enough to ignore the ART effect on TDD reduction.
   1. Determine growth surfaces and express them by equation(s). For instance, express the time evolution of a round-shaped cross-section of a SEG Ge layer with the time evolution parameter n = i, SEG Ge heights (h_i) and SEG Ge radii (r_i), as shown in the Supplemental Video 1a and Eq. (1):
      

Results

Theoretical Calculation

Figure 3 shows calculated trajectories of TDs in 6 types of coalesced Ge layers: here, we define the aperture ratio (APR) to be W_window/(W_window + W_mask). Figure 3a shows a round-shaped SEG origin coalesced Ge of APR = 0.8. Here, 2/6 TDs are trapped. Figure 3b shows a.......

Discussion

In the present work, TDD of 4 x 10⁷/cm² were experimentally shown. For further TDD reduction, there are mainly 2 critical steps within the protocol: SEG mask preparation and epitaxial Ge growth.

Our model shown in Figure 4 indicates that TDD can be reduced lower than 10⁷/cm² in coalesced Ge when APR, W_window/(W_window + W_mask), is as small as 0.1. Toward further TDD reduction, SEG masks wi.......

Materials

List of materials used in this article

Name	Company	Catalog Number	Comments
AFM	SII NanoTechnology	SPI-3800N
BHF	DAIKIN	BHF-63U
CAD design	AUTODESK	AutoCAD 2013	Software
CH3COOH	Kanto-Kagaku	Acetic Acid	for Electronics
CVD	Canon ANELVA	I-2100 SRE
Developer	ZEON	ZED
Developer rinse	ZEON	ZMD
EB writer	ADVANTEST	F5112+VD01
Furnace	Koyo Thermo System	KTF-050N-PA
HF, 0.5 %	Kanto-Kagaku	0.5 % HF
HF, 50 %	Kanto-Kagaku	50 % HF
HNO3, 61 %	Kanto-Kagaku	HNO3 1.38	for Electronics
I2	Kanto-Kagaku	Iodine 100g
Photoresist	ZEON	ZEP520A
Photoresist remover	Tokyo Ohka	Hakuri-104
Surfactant	Tokyo Ohka	OAP
TEM	JEOL	JEM-2010HC