In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VO_x

Summary

Presented here is a protocol for analyzing nanostructural changes during in situ biasing with transmission electron microscopy (TEM) for a stacked metal-insulator-metal structure. It has significant applications in resistive switching crossbars for the next generation of programmable logic circuits and neuromimicking hardware, to reveal their underlying operation mechanisms and practical applicability.

Abstract

Resistive switching crossbar architecture is highly desired in the field of digital memories due to low cost and high-density benefits. Different materials show variability in resistive switching properties due to the intrinsic nature of the material used, leading to discrepancies in the field because of underlying operation mechanisms. This highlights a need for a reliable technique to understand mechanisms using nanostructural observations. This protocol explains a detailed process and methodology of in situ nanostructural analysis as a result of electrical biasing using transmission electron microscopy (TEM). It provides visual and reliable evidence of underlying nanostructural changes in real time memory operations. Also included is the methodology of fabrication and electrical characterizations for asymmetric crossbar structures incorporating amorphous vanadium oxide. The protocol explained here for vanadium oxide films can be easily extended to any other materials in a metal-dielectric-metal sandwiched structure. Resistive switching crossbars are predicted to serve the programmable logic and neuromorphic circuits for next-generation memory devices, given the understanding of the operation mechanisms. This protocol reveals the switching mechanism in a reliable, timely, and cost-effective way in any type of resistive switching materials, and thereby predicts the device's applicability.

Introduction

Resistance change oxide memories are increasingly used as the building block for novel memory and logic architectures due to their compatible switching speed, smaller cell structure, and the ability to be designed in high capacity three-dimensional (3D) crossbar arrays¹. To date, multiple switching types have been reported for resistive switching devices^2,3. Common switching behaviors for metal oxides are unipolar, bipolar, complementary resistive switching, and volatile threshold switching. Adding on to the complexity, single cell has been reported to show multifunctional resistive switching performance as well^4,5,6.

This variability means that nanostructural investigations are needed to understand the origins of different memory behaviors and corresponding switching mechanisms to develop clearly defined condition-dependent switching for practical utility. Commonly reported techniques to understand the switching mechanisms are depth profiling with X-ray photoelectron spectroscopy (XPS)^7,8, nanoscale secondary ion mass spectroscopy (nano-SIMS)⁶, nondestructive photoluminescence spectroscopy (PL)⁸, electrical characterization of different size and thickness of functional oxide of devices, nanoindentation⁷, transmission electron microscopy (TEM), energy-dispersive X-ray spectroscopy (EDX), and electron energy loss spectroscopy (EELS) on cross-sectional lamella in a TEM chamber^6,8. All the above techniques have provided satisfactory insights about the switching mechanisms. However, in most of the techniques, more than one sample is required for analysis, including the pristine, electroformed, set, and reset devices, to understand the complete switching behavior. This increases experimental complexity and is time consuming. Additionally, the failure rates are high, because locating a subnanoscale filament in a device a few microns in size is tricky. Therefore, in situ experiments are important in nanostructural characterizations to understand operation mechanisms, as they provide evidence in real-time experiments.

Presented is a protocol for conducting in situ TEM with electrical biasing for metal-insulator-metal (MIM) stacks of asymmetric resistive switching cross-point devices. The primary goal of this protocol is to provide a detailed methodology for lamella preparation using a focus ion beam (FIB) and in situ experimental setup for TEM and electrical biasing. The process is explained using a representative study of asymmetric cross-point devices based on mixed-phased amorphous vanadium oxide (a-VO_x)⁴. Also presented is the fabrication process of cross-point devices incorporating a-VO_x, which can be easily scaled up to crossbars, using standard micro-nano fabrication processes. This fabrication process is important as it incorporates in crossbars a-VO_x which dissolves in water.

The advantage of this protocol is that with only one lamella, nanostructural changes can be observed in TEM, unlike the other techniques, where a minimum of three devices or lamellae are required. This significantly simplifies the process and reduces time, cost, and effort while providing reliable visual evidence of nanostructural changes in real-time operations. Additionally, it is designed with standard micro-nano fabrication processes, microscopy techniques, and instruments in innovative ways to establish its novelty and address the research gaps.

In the representative study described here for a-VO_x-based cross-point devices, the in situ TEM protocol helps to understand the switching mechanism behind apolar and volatile threshold switching⁴. The process and methodology developed for observing nanostructural changes in a-VO_x during in situ biasing can be easily extended to in situ temperature, and in situ temperature and biasing simultaneously, by just replacing the lamella mounting chip, and to any other material including two or more layers of functional material in a metal-insulator-metal sandwiched structure. It helps reveal the underlying operation mechanism and explain electrical or thermal characteristics.

Protocol

1. Fabrication process and electrical characterization

1. Use standard image reversal photolithography⁹ to pattern bottom electrode (BE layer 1) with photoresist of the devices using the following parameters:
   1. Spin coat the photoresist at 3,000 rpm, soft bake it at 90 °C for 60 s, expose with 25 mJ/cm² with a 405 nm laser, bake at 120 °C for 120 s, perform flood exposure with 21 mW/cm² and a 400 nm laser, develop using developer, and rinse with deionized water.
2. Deposit 5 nm titanium (Ti) for adhesion and 15 nm of platinum (Pt) on top with an electron beam evaporator system with the substrate patterned on layer 1.
3. Lift-off the deposited metals by placing the substrate in an acetone bath for ~20 mins. Then, apply ultrasonic vibrations for 2 min, and rinse with acetone and isopropyl alcohol (IPA) to complete the BE patterns. Repeat if the lift-off is not clean (Figure 1A, step 1).
4. Pattern the functional oxide layer (layer 2) with photolithography on top of the BE as described in step 1.1.
5. Deposit ~100 nm of a-VO_x and 5 nm of Ti on top of layer 2 using a sputtering system¹⁰.
6. Lift-off the functional oxide by placing the substrate in an acetone bath and applying pulsed ultrasonic vibrations manually with 2–3 s pulses to finalize the functional oxide patterns. Repeat the procedure if the patterns are not clean. (Figure 1A, step 2 and step 3)
7. Similarly, complete the top electrode (TE) (layer 3) patterns with Ti_20 nm/Pt_200 nm using image reversal photolithography, electron beam evaporation, and the lift-off process described in step 1. (Figure 1A, step 4)
   NOTE: This completes the fabrication of the cross-point device, Figure 1B.
8. Perform electrical and temperature analysis on the fabricated device to understand its resistance switching performance.
   1. Use the source meter with two-probe direct current (DC) I–V measurement system and a probe station for electrical measurements.
   2. Always maintain the relevant current compliance to avoid damaging the devices.
   3. To analyze the device's current behavior, perform voltage-controlled analysis and apply voltage sweeps starting with a low voltage of 0.1 V in positive bias and increasing slowly until electroforming is observed.
      NOTE: Electroforming is a one-time event at which a few nanometer-wide conductive filaments are formed within the initially insulating functional oxide at a particular voltage, which depends on intrinsic material properties and device dimensions. At this point, a sudden drop in resistance or increase in current is observed on the current-voltage graph due to a formed conductive path.
   4. After electroforming, apply bidirectional voltage sweeps to achieve volatile threshold switching performance. Adjust the voltage to achieve a high ON/OFF ratio. In this case, a switching ratio of ~10 was attained.
   5. Analyze the current-voltage characteristics at different temperatures from room temperature to 90 °C increasing in 10 °C steps and reverse back to room temperature using a temperature-controlled stage.

2. Gridbar and biasing chip mounting

1. Design the FIB optimized gridbar in CAD software and manufacture using standard machining techniques in-house for mounting the biasing/heating chips used for in situ TEM experiments, as shown in Figure 2.
   NOTE: Figure 2A shows separate parts of the gridbar to mount three chips simultaneously in the square shaped trenches. Figure 2B shows the zoomed squared trench section designed to fit the commercially available in situ biasing/heating chips for TEM.
2. Clean the biasing chip by placing it in a glass Petri dish filled with acetone and gently rotate for 2 min. Then remove the chip and place it in a Petri dish filled with methanol and gently rotate for 2 min. Finally, blow dry with low pressured nitrogen.
   NOTE: Commercially bought biasing chips, referred to as E-chips, have a photoresist coating for protection.
3. Align the precleaned biasing chip in square trenches of gridbar, as seen in Figure 2C.
4. Fix the grid cover on top of the biasing chip with screws to finalize the placement of the E-chip on the gridbar (Figure 2D).

3. Lamella preparation, mounting on biasing chip using focused ion beam, and in situ transmission electron microscopy

1. Fabricate the samples separately as described in section 1 with a thicker BE of Ti_10 nm/Pt_100 nm, as seen in Figure 3A.
2. Mount the newly prepared sample on a metal stub using conductive carbon tape and load in the FIB chamber. Apply additional tape on the sample for grounding to avoid charging problems.
3. Load the biasing chip-mounted gridbar in the chamber at a 52° tilt (see Figure 3B). This will be either perpendicular or parallel to the ion beam column depending on the stage rotation.
4. Focus, astigmate, and align the electron beam on a sample surface using the microscope physical control panel and software on lamella preparation locations.
5. Check the eucentric height of the focused sample location and beam coincidence for the electron beam and ion beam.
   NOTE: The eucentric height is the position where the sample’s image does not move when the sample is tilted.
6. Click on Auto TEM program (automatic lamella preparation program) to run it on the focused sample location using the microscope control software. The automatic program follows the sequence described below.
   NOTE: This will complete the process for creating a TEM lamella (Figure 4). The progress of the AutoTEM program can be observed live on the desktop screen.
   1. Create cross fiducial alignment markers with silicon milling and deposit a 1.5 µm-thick carbon protective layer over the 20 µm x 5 µm area between alignment markers.
   2. Mill trenches on either side of carbon protective layer with a 5 nA ion beam current to create the lamella.
   3. Thin the lamella with a 1 nA ion beam current first and then with 300 pA ion beam current to reach a 1 µm thickness.
7. Tilt the sample to 7° to perform a J-cut on the lamella for separation from the substrate.
8. Tilt the sample to 0° (i.e., perpendicular to the electron beam column) and attach the lamella to the manipulator needle by wielding using Pt (Figure 5A).
9. After attachment to the micromanipulator, separate the lamella from the substrate with the final cut and slowly retract the micromanipulator (Figure 5B).
10. Focus the beam on the top edge of biasing chip on the gridbar, the lamella mounting position.
11. Bring the lamella slowly towards the biasing chip with the manipulator needle (Figure 6A).
12. Align the lamella in the center of the 17 µm gap on the top edge of the biasing chip. Slowly move it down until it barely touches the chip surface and weld the bottom edges of the lamella to the chip using Pt (Figure 6B).
13. Cut the micromanipulator free from the lamella with silicon milling and retract the micromanipulator.
14. Connect the top edges of the lamella with Pt traces to the two electrodes of the biasing chip for electrical connections (Figure 6C).
    NOTE: The TE and BE are shorted at this point on both left and right sides.
15. Thin the center region of lamella first using 300 pA, and then with 100 pA ion beams to make the lamella less than 100 nm thick (Figure 6D) by tilting the specimen front and back by 2° to ensure parallel faces and a uniform thickness.
16. Polish out the ion beam-damaged layer with the Ga beam accelerating voltage of 5 kV at an angle of 5° to the surface on both faces.
17. Remove the short connection between the top and bottom electrodes of the device with isolation cuts in the thinned region to create a current path from BE to TE through the active region (Figure 7A).
18. Mount the biasing chip with lamella on the biasing chip holder and then load the biasing chip holder into the TEM chamber.
19. Connect the wires from the biasing chip holder to the source meter and a control PC.
    NOTE: Carefully place the connection wires to relieve the strain and minimize any vibrations during the experiment.
20. Wait for the TEM chamber pressure to drop to 4e-5 Torr and then focus, astigmate, and align the electron beam on a cross section of the lamella surface using the TEM control knobs.
21. Apply voltage sweeps or constant voltage at different biasing voltages and collect the TEM micrographs in situ.
    NOTE: Data related to diffraction patterns, electron diffraction X-ray spectroscopy (EDX), and electron energy loss spectroscopy (EELS) mapping can also be collected at different biasing voltages in situ.

Representative Results

The results achieved using this protocol for the a-VO_x cross-point devices are explained in Figure 8. Figure 8A shows the TEM micrograph of the intact lamella. Here the diffraction patterns (inset) indicate the amorphous nature of the oxide film. For the in situ TEM measurements, controlled voltages were applied starting from 25 mV to 8 V in 20 mV steps with the bottom electrode (BE) positively biased and top electrode (TE) grounded. Figure 8B shows that at 4 V a localized crystalline region formed in the oxide layer. Here, d-spacing was 0.35 nm, as shown in the high-resolution TEM (HRTEM) and diffraction patterns (insets). This d-spacing corresponds to the (011) plane of the VO₂–M1 phase^10,11. Figure 8C shows the multiple localized crystal islands within the oxide layer at 5 V. These crystal islands were oriented in different directions with respect to the substrate. Two different d-spacings can be observed in the corresponding FFT and HRTEM (insets): 0.35 nm and 0.27 nm. A spacing of 0.27 nm corresponds to the VO₂–A phase, while 0.26 nm corresponds to the VO₂–M1 phase¹². Considering the aberration defects and tilt correction limits of the instrument, the observed 0.27 nm d-spacing likely corresponds to the mixed phase of VO₂–M1 and VO₂–A. Figure 8D shows the Moiré fringes at 6 V. There are multiple nucleation sites in the lamella. Here FFT and HRTEM (insets) provide further evidence of the different orientations of the VO₂–M1 crystal islands. After 6 V, the lamella is completely crystallized with multiple orientations only with the electrical bias without any conventional annealing.

This is the first demonstration of a-VO_x thin film crystallizing into localized c-VO₂ islands with electric bias. The strong evidence for the presence of c-VO₂ islands in a-VO_x devices after biasing at higher voltage proves the resistive switching characteristics (Figure 2 of cited reference⁴) and the switching mechanism (Figure 6 of the cited reference⁴) for asymmetric cross-point devices based on mixed-phased a-VO_x.

The results show the application of the explained protocol. Here the in situ nanostructural changes were captured in remanence of voltage sweeps at different voltages with the high-resolution TEM (HRTEM) micrographs and corresponding diffraction patterns.

Figure 1: Fabrication flow and cross-point device structure schematic. (A) Fabrication flow incorporating Ti capping to protect a-VO_x film from dissolving in water. (B) Schematic of cross-point device structure. This figure has been modified from Nirantar et al.⁴. Please click here to view a larger version of this figure.

Figure 2: Custom-made FIB optimized gridbar for in situ mounting of TEM chips. (A) Individual parts of the gridbar. (B) Squared trench for in situ TEM chip placement. (C) Aligned biasing chip for in situ TEM in the squared trench. (D) Mounted biasing chip on the gridbar. Please click here to view a larger version of this figure.

Figure 3: Cross section stacks for in situ samples and FIB chamber setup of biasing chip. (A) Cross section stacks of devices prepared separately for in situ biasing using TEM sample. (B) Gridbar setup in the chamber to allow access to the scanning electron microscopy (STEM) detector for precision cutting and connections on the lamella. Please click here to view a larger version of this figure.

Figure 4: Processing steps of Auto TEM. (A) Alignment markers and protection layer deposition. (B) Trenches formed with rough milling using a 5 nA current. Please click here to view a larger version of this figure.

Figure 5: The process of lamella separation from the substrate. (A) Manually made J-cut and attached lamella to the manipulator needle. (B) Extracted lamella through the trenches after the final separation cut. Please click here to view a larger version of this figure.

Figure 6: Lamella mounting on the biasing chip process. (A) Manipulator bringing the attached lamella to the biasing chip. (B) Lamella attached to the biasing chip. (C) Connections with platinum traces between the electrodes of the biasing chip and the region of interest of the lamella. (D) Sub-100 nm thinned center region of the lamella. Please click here to view a larger version of this figure.

Figure 7: Final isolation cuts and the current path in the lamella and micrograph of the FIB optimized biasing chip. Please click here to view a larger version of this figure.

Figure 8: In situ electrical transmission electron microscopy. (A) Original lamella. The inset shows the FFT of the functional layer. (B) Micrograph after 4 V biasing. FFT inset shows c-VO₂ (M1) phase with (011) plane and HRTEM inset shows the fringes separation as 0.35 nm. (C) Micrograph after 5 V. FFT and HRTEM insets show multiple nucleation sites and different orientations of the same c-VO₂–M1. (D) Micrograph after 6 V. FFT inset shows different orientations of same c-VO₂ – M1 phase. HRTEM inset shows the formation of Moiré fringes. This figure has been modified from Nirantar et al.⁴. Please click here to view a larger version of this figure.

Discussion

This paper explains the protocol for in situ biasing with transmission electron microscopy including the fabrication process for the device, gridbar designing for biasing chip mounting, lamella preparation and mounting on the biasing chip, and TEM with in situ biasing.

The fabrication methodology of cross-point devices, which can be easily scaled up to crossbar structures, is explained. The Ti capping of vanadium oxide is essential to incorporate amorphous vanadium oxide, because it dissolves in water during the fabrication steps after a-VO_x deposition. Devices are fabricated with two different sizes for electrical testing, 4 µm x 4 µm and 6 µm x 6 µm. The contact electrode used here is Pt, a noble metal that degrades minimally over the fabrication period. Due to this and to avoid the uniform crystallization of vanadium oxide in the device structure, the electrode annealing step typically used was omitted in this fabrication method. A complete fabrication flow and the device structure schematic is presented Figure 1⁴.

For in situ experiments, the devices are fabricated separately with thicker BE as explained in step 1 of the lamella preparation and mounting on biasing chip section. This is done to avoid the deposition of Pt particles on the functional layer during connections. The change in thickness of the BE is not expected to have an effect in device switching.

The commercially available biasing chips (e.g., E-chip) for in situ biasing with TEM have four biasing electrodes available for connection and a 17 µm wide gap for mounting the lamella, as shown in Figure 7B. A customized gridbar is designed to mount the biasing chips, as this arrangement allows access to the scanning transmission electron microscopy (STEM) detector in the FIB chamber for precise cutting and connection of the lamella mounted on the biasing chip. This is especially required for the precise isolation cuts explained in step 17 of the lamella preparation and mounting on the biasing chip section. For the lamella preparation and mounting process, the sequence of Pt connections, lamella thinning, and making isolation cuts (steps 14–17 of lamella preparation and mounting) are the most critical to achieve a clean lamella. Here, the Pt connecting traces are performed before the thinning process to avoid deposition of Pt particles on the functional oxide layer, which can ruin electrical attributes.

As the lamella is prepared using Ga ion milling, some undesirable Ga contamination is expected in the final lamella. However, lamella polishing is performed to significantly reduce the damage caused by the Ga beam. Another drawback of this protocol is that the dimensions of the lamella are significantly smaller (in nanoscale) compared to the actual device (a few microns). Due to this, variability can be observed in the electrical characterizations of the actual device and the lamella-based device.

Despite of that, this protocol offers a significant advantage over the existing techniques as it provides visual verification of every step of the lamella preparation and during the in situ biasing. As all the steps can be seen visually in real time, failures are detected and rectified immediately. There are no hidden aspects in the process and troubleshooting is simply by visual observation unless there are any instrument specific issues.

The presented methodology has a notable impact in the field of material science and resistive switching devices compatible with high vacuum conditions. The protocol can explain the electrical results and operation mechanisms based on visually observed nanostructural changes in situ. This protocol will influence next generation of nanoelectronics, logic circuits, neuromorphic devices, and material sciences to reveal the underlying operation mechanisms and predict the practical applicability of novel structures and materials.

Materials

Name	Company	Catalog Number	Comments
Resist processing system	EV group	EVG 101
Acetone	Chem-Supply	AA008
Biasing Chip - E-chip	Protochips	E-FEF01-A4
Developer	MMRC	AZ 400K
Electron beam evaporator - PVD 75	Kurt J Leskar	PRO Line - eKLipse
Focused Ion beam system	Thermo Fisher - FEI	Scios DualBeamTM system
Hot plates	Brewer Science Inc.	1300X
Magnetron Sputterer	Kurt J Leskar	PRO Line
Mask aligner	Karl Suss	MA6
Maskless Aligner	Heildberg instruments	MLA150
Methanol	Fisher scientific	M/4056
Phototresist	MMRC	AZ 5412E
Pt source for e-beam evaporator	Unicore
The Fusion E-chip holder	Protochips	Fusion 350
Ti source for e-beam evaporator	Unicore
Transmission Electron Microscope	JEOL	JEM 2100F