Name: Developing High Performance GaP/Si Heterojunction Solar Cells (Video) | JoVE Journal
Uploaded: 2018-11-16T15:00:00.000+00:00
Duration: 10 min 31 s
Description: Learn to fabricate high-performance GaP/Si heterojunction solar cells while maintaining long silicon minority-carrier lifetime. This protocol enables efficient multijunction devices with optimized carrier selective contacts.

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5 minutes

The authors would like to thank L. Ding and M. Boccard for their contributions in processing and testing of the solar cells in this study. The authors acknowledge funding from the U.S. Department of Energy under contract DE-EE0006335 and the Engineering Research Center Program of the National Science Foundation and the Office of Energy Efficiency and Renewable Energy of the Department of Energy under NSF Cooperative Agreement No. EEC-1041895.&#160;Som Dahal at Solar Power Lab was supported, in part, by NSF contract ECCS-1542160.

CAUTION: Please consult all relevant material safety data sheets (MSDS) before dealing with chemicals. Please use all appropriate safety practices when performing a solar cell fabrication including the fume hood and personal protective equipment (safety glasses, gloves, lab coat, full-length pants, closed-toe shoes).
1. Si Wafer Cleaning
<ol>
	<li>Clean Si wafers in Piranha solution (H2O2/H2SO4) at 110 &#176;C.
	<ol>
		<li>To produce Piranha solution, fill the acid bath (high-density polyethylene tank and hereafter) with 15.14 L of H2SO4 (96%) and then 1.8 L of H2O2 (30%).</li>
		<li>Wait for the temperature of the solution to stabilize at 110 &#176;C.</li>
		<li>Place 4-inch-diameter, float-zone (FZ), n-type, and double-side-polished Si wafers in a clean 4&#8221; wafer cassette (polypropylene and hereafter), and place the boat in the Piranha bath for 10 min.</li>
		<li>Rinse for 10 min with deionized (DI) water.</li>
	</ol>
	</li>
	<li>Clean Si wafers with RCA cleaning solution at 74 &#176;C.
	<ol>
		<li>Prepare a diluted solution of HCl:H2O2. Fill the acid bath with 13.2 L of DI H2O and 2.2 L of HCl. Spike the solution with 2.2 L of H2O2 and turn on the heater.</li>
		<li>Wait for the temperature of the solution to stabilize at 74 &#176;C before use.</li>
		<li>Put Si wafers in a clean 4&#8221; wafer cassette and place wafers in the RCA solution for 10 min.</li>
		<li>Rinse with DI water for 10 min.</li>
	</ol>
	</li>
	<li>Clean Si wafers in Buffered Oxide Etch (BOE) solution.
	<ol>
		<li>Pour 15.14 L of BOE solution in the acid bath.</li>
		<li>Place the 4&#8221; wafer cassette in the bath for 3 min.</li>
		<li>Rinse for 10 min with DI water.</li>
		<li>Dry the wafer by dry N2.</li>
	</ol>
	</li>
</ol>
2. P-diffusion in the Diffusion Furnace
<ol>
	<li>Put a cleaned wafer in a diffusion quartz boat.</li>
	<li>Load it into a quartz tube that has a base temperature of 800 &#176;C. Ramp the furnace temperature to 820 &#176;C in the N2 environment. At 820 &#176;C, start flowing the N2 carrier gas that bubbles through phosphorous oxychloride (POCl3) at 1000 sccm. After 15 min, turn off the N2 carrier gas and ramp the temperature down to 800 &#176;C before taking the samples out.</li>
	<li>Place the samples in a BOE solution for 10 min to remove phosphorus silicate glass (PSG) and then perform a 10-min rinse in DI water.</li>
</ol>
3. SiNx coating by PECVD
<ol>
	<li>Put the wafer in a clean boat and dip it in a BOE bath for 1 min to remove the native oxide on the surface.</li>
	<li>Rinse for 10 min with DI water.</li>
	<li>Dry the wafer with a dry N2 gun.</li>
	<li>Place the Si wafer on a clean Si carrier (156 mm monocrystalline Si).</li>
	<li>Load the sample into the plasma enhanced chemical vapor deposition (PECVD) chamber.</li>
	<li>Deposit 150 nm-thick (38.5 s) SiNx at 350 &#176;C in the chamber. Deposit SiNx at 300 W RF power with a base pressure of 3.5 Torr and 60 sccm of SiH4 as a silicon source and 60 sccm of NH3 as a N source (2000 sccm of N2 was used as a diluent).
	<ol>
		<li>Confirm the growth rate of SiNx (3.9 nm/s) by depositing SiNx films with different deposition times on polished wafers and measure the thicknesses by variable angle spectroscopic ellipsometry (VASE).</li>
	</ol>
	</li>
</ol>
4. GaP Growth by MBE
<ol>
	<li>After SiNx deposition, load the wafer into the MBE chamber.</li>
	<li>Outgas in the introductory chamber (180 &#176;C for 3 h), then outgas in the buffer chamber (240 &#176;C for 2 h). Load in to the growth chamber and bake at 850 &#176;C for 10 min.</li>
	<li>Decrease temperature to 580 &#176;C. Increase Ga effusion cell temperature to produce ~2.71&#215;10-7 Torr beam-equivalent pressure (BEP) and Si effusion cell temperature to 1250 &#176;C.</li>
	<li>Adjust the p-valved cracker positioner to achieve ~1.16&#215;10-6 Torr BEP. Open the Ga, P, and Si shutters and grow 25 nm-thick GaP with an interrupted growth method (10 cycles of 5 s open and 5 s closed) followed by 121 s of unshuttered growth (i.e., open Ga and p shutters simultaneously).</li>
	<li>Decrease the substrate temperature to 200 &#176;C and unload the sample from the vacuum chamber.</li>
</ol>
5. Remove Back n+ and SiNx Layers by Wet Etching
<ol>
	<li>Cover the GaP surface with a protective tape to protect it from the HF damage.</li>
	<li>Prepare ~300 mL of 49% HF solution in a plastic beaker.</li>
	<li>Place the sample in the HF solution for 5 min to fully remove the SiNx layer.</li>
	<li>Remove the protective tape, rinse with DI water, and dry by N2.</li>
	<li>Cover the GaP surface with a new protective tape.</li>
	<li>Prepare HNA solution in a plastic beaker (a mixture of hydrofluoric acid (HF) (50 mL), nitric acid (HNO3) (365 mL), and acetic acids (CH&#173;3COOH) (85 mL)) at room temperature. 
	CAUTION: Carefully place the wafer in the solution to avoid HNA penetrating into the GaP surface.</li>
	<li>Put the sample in the HNA solution for 3 min.</li>
	<li>Remove the protective tape and rinse by DI water. Dry by N2.</li>
</ol>
6. Hole-Selective Contact Formation on the Bare Si Side
<ol>
	<li>Cleave the wafer with a diamond pen into four quarters.</li>
	<li>Thoroughly clean the samples in a DI water tank.</li>
	<li>Clean the samples in a BOE bath for 30 s to remove the native oxide from the surface.</li>
	<li>Rinse in the wafers in DI water and then dry by N2.</li>
	<li>Deposit a 50 nm-thick a-Si: H by PECVD on one of the samples to check the Si lifetime.
	<ol>
		<li>Deposit the a-Si: H layer at 60 W RF power with a pressure of 3.2 Torr and 40 sccm of SiH4 as the silicon source (200 sccm of H2 was used as a diluent).</li>
		<li>Confirm the growth rate of a-Si: H (1.6 nm/s) by depositing a-Si films with different deposition times on polished wafers and measuring the thickness with VASE.</li>
	</ol>
	</li>
	<li>Deposit (i)a-Si (9 nm) and (p+)a-Si (16 nm) on the etched (front) side of a separate Si sample by PECVD.
	<ol>
		<li>Deposit the p-type a-Si layer at 37 W RF power with a pressure of 3.2 Torr and 40 sccm of SiH4 as the silicon source and 18 sccm of B[CH3]3 as the boron dopant (197 sccm of H2 was used as a diluent).</li>
		<li>Confirm the growth rate of p-type a-Si (2.0 nm/s) by depositing a-Si films with different growth times on the polished wafers and measuring the thicknesses with VASE.</li>
	</ol>
	</li>
	<li>Deposit a 9 nm-thick MoOx layer at the room temperature by the thermal evaporation from a MoO3 (99.99%) source with a deposition rate of 0.5 &#197;/s.</li>
</ol>
7. External Contact Formation
<ol>
	<li>Deposit 75 nm-thick Indium Tin Oxide (ITO) (In2O3/SnO2 = 95/5 (weight percent), 99.99%) layers on the GaP side of the samples by RF sputtering (RF power of 1 kW and pressure of 5 Torr) with an oxygen flow rate of 2.2 sccm.</li>
	<li>Unload the samples and turn them over. Then use the mesa shadow mask on the samples for ITO mesa deposition.</li>
	<li>Deposit 75 nm-thick ITO by RF sputtering. Deposit 200 nm-thick silver (RF power of 1 kW and pressure of 8 Torr) for the fingers covering the finger shadow mask. Deposit 200 nm-thick silver on the GaP side of the samples as the back contact.</li>
	<li>Anneal the samples in a furnace under atmospheric pressure at 220 &#176;C.</li>
</ol>

<ol><li>Friedman, D. J. <a target="_blank" href="https://www.sciencedirect.com/science/article/pii/S135902861000032X">Progress and challenges for next-generation high-efficiency multijunction solar cells.</a> Current Opinion in Solid State & Materials Science. 14, 131-138 (2010).</li>
<li>Vadiee, E., et al. <a target="_blank" href="https://ieeexplore.ieee.org/abstract/document/8063407/">AlGaSb-Based Solar Cells Grown on GaAs: Structural investigation and device performance.</a> IEEE Journal of Photovoltaics. , (2017).</li>
<li>Wagner, H., et al. <a target="_blank" href="https://aip.scitation.org/doi/abs/10.1063/1.4863464">A numerical simulation study of gallium-phosphide/silicon heterojunction passivated emitter and rear solar cells.</a> Journal of Applied Physics. 115, 044508(2014).</li>
<li>Limpert, S., et al. <a target="_blank" href="https://ieeexplore.ieee.org/abstract/document/6925045/">Results from coupled optical and electrical sentaurus TCAD models of a gallium phosphide on silicon electron carrier selective contact solar cell.</a> 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC). , 836-840 (2014).</li>
<li>Ding, L., et al. <a target="_blank" href="https://ieeexplore.ieee.org/abstract/document/7749989/">On the source of silicon minority-carrier lifetime degradation during molecular beam heteroepitaxial growth of III-V materials.</a> 2016 IEEE 43rd Photovoltaic Specialists Conference (PVSC). , IEEE. 2048-2051 (2016).</li>
<li>Ding, L., et al. <a target="_blank" href="https://www.sciencedirect.com/science/article/pii/S1876610216304544">Silicon minority-carrier lifetime degradation during molecular beam heteroepitaxial III-V material growth.</a> Energy Procedia. 92, 617-623 (2016).</li>
<li>Zhang, C., Kim, Y., Faleev, N. N., Honsberg, C. B. <a target="_blank" href="https://www.sciencedirect.com/science/article/pii/S0022024817304025">Improvement of GaP crystal quality and silicon bulk lifetime in GaP/Si heteroepitaxy.</a> Journal of Crystal Growth. 475, 83-87 (2017).</li>
<li>García-Tabarés, E., et al. <a target="_blank" href="https://onlinelibrary.wiley.com/doi/abs/10.1002/pip.2703">Evolution of silicon bulk lifetime during III-V-on-Si multijunction solar cell epitaxial growth.</a> Progress in Photovoltaics: Research and Applications. 24, 634-644 (2016).</li>
<li>Varache, R., et al. <a target="_blank" href="https://www.sciencedirect.com/science/article/pii/S1876610215008383">Evolution of bulk c-Si properties during the processing of GaP/c-Si heterojunction cell.</a> Energy Procedia. 77, 493-499 (2015).</li>
<li>Ishizaka, A., Shiraki, Y. <a target="_blank" href="http://jes.ecsdl.org/content/133/4/666.short">Low temperature surface cleaning of silicon and its application to silicon MBE.</a> Journal of The Electrochemical Society. 133, 666(1986).</li>
<li>Zhang, C., Vadiee, E., King, R. R., Honsberg, C. B. <a target="_blank" href="https://www.cambridge.org/core/journals/journal-of-materials-research/article/carrierselective-contact-gapsi-solar-cells-grown-by-molecular-beam-epitaxy/E5A9209E449CFCF2C4479752764CA400">Carrier-selective contact GaP/Si solar cells grown by molecular beam epitaxy.</a> Journal of Materials Research. 33, 414-423 (2018).</li>
<li>Battaglia, C., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Hole+Selective+MoOx+Contact+for+Silicon+Solar+Cells%5BTitle%5D)+AND+%22Nano+Letters%22%5BJournal%5D)">Hole Selective MoOx Contact for Silicon Solar Cells.</a> Nano Letters. 14, 967-971 (2014).</li>
</ol>

The authors have nothing to disclose.

A nominal 25 nm-thick GaP layer was epitaxially grown on a P-rich Si surface via MBE. To grow a better quality of GaP layer on Si substrates, a relatively low V/III (P/Ga) ratio is preferable. A good crystal quality of GaP layer is necessary to achieve high conductivity and low density of recombination centers. The AFM root-mean-square (RMS) of the GaP surface is ~0.52 nm showing a smooth surface with no pits, indicative of high crystal quality with a low threading dislocation density (Figure 1a</str...

There has been a continuing effort on the integration of different materials with lattice mismatches in order to enhance overall solar cell efficiency1,2. The III-V/Si integration has the potential to further increase the current Si solar cell efficiency and replace the expensive III-V substrates (such as GaAs and Ge) with a Si substrate for multijunction solar cell applications. Among all III-V binary material systems, gallium phosphide (GaP) is a good candidate for this purpose, as it has the smallest lattice-mismatch (~0.4%) with Si and a high indirect bandgap. These features can enable high-quality integration of GaP with Si substrate. It has been theoretically shown that GaP/Si heterojunction solar cells could enhance the efficiency of conventional passivated emitter rear Si solar cells3,4 by benefiting from the unique band-offset between GaP and Si (&#8710;Ev ~1.05 eV and &#8710;Ec ~0.09 eV). This makes GaP a promising electron selective contact for silicon solar cells. However, in order to achieve high-performance GaP/Si heterojunction solar cells, a high Si bulk lifetime and high GaP/Si interface quality are required.
During the growth of III-V materials on a Si substrate by molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE), significant Si lifetime degradation has been widely observed5,6,7,8,9. It was revealed that the lifetime degradation mainly happens during the thermal treatment of the Si wafers in the reactors, which is required for surface oxide desorption and/or surface reconstruction before the epitaxial growth10. This degradation was ascribed to the extrinsic diffusion of contaminants originated from the growth reactors5,7. Several approaches have been proposed to suppress this Si lifetime degradation. In our previous work, we have demonstrated two methods in which the Si lifetime degradation can be significantly suppressed. The first method was demonstrated by the introduction of SiNx as a diffusion barrier7 and the second one by introducing the P-diffusion layer as a gettering agent11 to the Si substrate.
In this work, we have demonstrated high-performance GaP/Si solar cells based on the aforementioned approaches to mitigate the silicon bulk lifetime degradation. The techniques used to preserve the Si lifetime can have broad applications in multijunction solar cells with active Si bottom cells and electronic devices such as high-mobility CMOS. In this detailed protocol, the fabrication details of GaP/Si heterojunction solar cells, including Si wafer cleaning, P-diffusion in the furnace, GaP growth, and GaP/Si solar cells processing, are presented.

<table><tbody><tr><td>Hydrogen peroxide, 30%</td><td>Honeywell</td><td>10181019</td><td></td></tr><tr><td>Sulfuric acid, 96%</td><td>KMG electronic chemicals, Inc.</td><td>64103</td><td></td></tr><tr><td>Hydrochloric acid, 37%</td><td>KMG electronic chemicals, Inc.</td><td>64009</td><td></td></tr><tr><td>Buffered Oxide Etch 10:1</td><td>KMG electronic chemicals, Inc.</td><td>62060</td><td></td></tr><tr><td>Hydrofluoric acid, 49%</td><td>Honeywell</td><td>10181736</td><td></td></tr><tr><td>Acetic acid</td><td>Honeywell</td><td>10180830</td><td></td></tr><tr><td>Nitride acid, 69.5%</td><td>KMG electronic chemicals, Inc.</td><td>200288</td><td></td></tr></tbody></table>

developing high performance gap/si heterojunction solar cells

Developing High Performance GaP/Si Heterojunction Solar Cells

To improve the efficiency of Si-based solar cells beyond their Shockley-Queisser limit, the optimal path is to integrate them with III-V-based solar cells. In this work, we present high performance GaP/Si heterojunction solar cells with a high Si minority-carrier lifetime and high crystal quality of epitaxial GaP layers. It is shown that by applying phosphorus (P)-diffusion layers into the Si substrate and a SiNx layer, the Si minority-carrier lifetime can be well-maintained during the GaP growth in the molecular beam epitaxy (MBE). By controlling the growth conditions, the high crystal quality of GaP was grown on the P-rich Si surface. The film quality is characterized by atomic force microscopy and high-resolution x-ray diffraction. In addition, MoOx was implemented as a hole-selective contact that led to a significant increase in the short-circuit current density. The achieved high device performance of the GaP/Si heterojunction solar cells establishes a path for further enhancement of the performance of Si-based photovoltaic devices.

Atomic force microscopy (AFM) images and high-resolution x-ray diffraction (XRD) scans, including the rocking curve in the vicinity of the (004) reflection and the reciprocal space map (RSM) in the vicinity of (224) reflection, were collected for the GaP/Si structure (Figure 1). The AFM was used to characterize the surface morphology of the MBE-grown GaP and XRD was used to examine the crystal quality of GaP layer. The effective minority-carrier lifetime of t...

Here, we present a protocol to develop high-performance GaP/Si heterojunction solar cells with a high Si minority-carrier lifetime.

To improve the efficiency of Si-based solar cells beyond their Shockley-Queisser limit, the optimal path is to integrate them with III-V-based solar ...

developing-high-performance-gapsi-heterojunction-solar-cells

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Learn to fabricate high-performance GaP/Si heterojunction solar cells while maintaining long silicon minority-carrier lifetime. This protocol enables efficient multijunction devices with optimized carrier selective contacts.

Developing High Performance GaP/Si Heterojunction Solar Cells

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