Developing High Performance GaP/Si Heterojunction Solar Cells

This method can tell, answer key questions in stratified silicon integrated solar cell fabrication about how to maintain a high silicon bulk lifetime during the growth. The main advantages of this process are that we can achieve a long silicon bulk lifetime, even after heterovalent growth of the gallium phosphide carrier selective contact on silicon. This allows us to access the band gaps of other III-V semiconductors.

It's a form of multijunction solar cell with a silicon bottom cell. To begin, prepare a piranha solution in a high-density polyethylene acid heating bath, heating it to 110 degrees Celsius, and wait for the temperature to stabilize. In another acid bath, prepare a diluted hydrochloric acid and hydrogen peroxide solution for removing ionic contamination, heating it to 74 degrees Celsius and waiting for the temperature to stabilize.

Place four inch diameter float zone end type double side polished silicon wafers in a clean polypropylene four inch wafer cassette. Soak the wafers in piranha solution for 10 minutes. Then, rinse the wafers for 10 minutes with deionized water, and put them in a clean cassette.

Soak the wafers in the ionic cleaning solution for 10 minutes, and then rinse them with deionized water for 10 minutes. Then, soak the wafers in a buffered oxide etch solution of 10 to one ammonium fluoride to hydrofluoric acid for three minutes at room temperature, and rinse them with deionized water for 10 minutes. Dry the clean wafers under a stream of dry nitrogen gas.

Next, place a clean wafer in a quartz boat and load it into a quartz tube furnace, heated to 800 degrees Celsius with an atmosphere of flowing nitrogen gas. Ramp the furnace to 820 degrees Celsius over the course of 20 minutes. Then, switch the carrier gas to nitrogen bubbled through phosphorus oxychloride at 1, 000 SCCM.

After 15 minutes, stop the flow of carrier gas and ramp the furnace down to 800 degrees Celsius. Remove the wafer from the furnace and let it cool. Then, soak it in fresh buffered oxide etch solution for 10 minutes to remove phosphorus silicate glass.

Rinse the wafer in deionized water for 10 minute and dry it with nitrogen gas. Just before the silicon nitride deposition, soak the wafer in a buffered oxide etch solution for one minute to remove native oxides. Rinse it in deionized water for 10 minutes, and dry it with dry nitrogen gas.

Place the wafer on a clean monocrystalline silicon carrier and load it into a PECVD instrument, equipped with silane and ammonia sources. Set the chamber pressure to 3.5 torrs and deposit 150 nanometers of silicon nitride at 3.9 nanometers per second, with 300 watts of RF power. Next, load the wafer into an MBE instrument, equipped with gallium, phosphorus, and silicon effusion cells.

Outgas the wafer in the introductory chamber at 180 degrees Celsius for three hours. Then, transfer the wafer to the buffer chamber, and outgas it at 240 degrees Celsius for two hours. Load the wafer into the growth chamber, and bake it at 850 degrees Celsius for 10 minutes.

After that, cool the wafer to 580 degrees Celsius, and prepare the effusion cells to generate the appropriate fluxes. Open the gallium, phosphorus, and silicon shudders, and grow 25 nanometers of gallium phosphide with an interrupted growth method, followed by 121 seconds of uninterrupted growth. Afterwards, cool the sample to 200 degrees Celsius and unload it from the instrument.

Next, cover the gallium phosphide surface with an acid-resistant dicing tape. Soak the wafer in about 300 milliliters of 49%hydrofluoric acid for five minutes to remove the silicon nitride layer. Remove the tape, rinse the wafer with deionized water for 10 minutes, and dry it under a stream of nitrogen gas.

Then, cover the gallium phosphide surface with fresh dicing tape. In a plastic beaker, prepare 500 milliliters of a mixture of hydrofluoric acid, nitric acid, and acetic acid. Carefully place the wafer in the HNA solution and let it soak at room temperature for three minutes.

Remove the tape, rinse the wafer with deionized water, and dry it with nitrogen. Use a diamond pen to slice the prepared wafer into four quarters. Place the pieces in a basket, thoroughly clean them in a tank of deionized water, and dry them with nitrogen gas.

Then, soak the pieces in a buffered oxide etch solution for 30 seconds, and rinse and dry them with deionized water and nitrogen gas. Next, deposit 50 nanometers of amorphous silicon on one sample, and check the silicon lifetime. Then, deposit nine nanometers of an intrinsic amorphous silicon, and 16 nanometers of a p-type amorphous silicon, with a boron dopant, on the bare silicon side of a second sample.

On a third sample, use thermal evaporation to deposit nine nanometers of molybdenum oxide on the bare silicon side at 0.5 angstroms per second, at room temperature, from a molybdenum trioxide source. Next, place the amorphous silicon and molybdenum oxide-coated samples in an RF sputtering instrument, with the gallium phosphide side facing up. Deposit 75 nanometers of indium 10 oxide, with an oxygen flow rate of 2.2 SCCM.

Then, unload the samples and turn them over. Place a mesa shadow mask on each sample. Load them back into the instrument, and deposit another 75 nanometers of ITO.

Unload the samples, exchange the mask for a finger shadow mask, and deposit 200 nanometers of silver on the ITO mesa at one kilowatt and eight torr. Turn over the samples and deposit another 200 nanometers of silver on the ITO gallium phosphide side, as the back contact. Lastly, anneal the samples in a furnace at 220 degrees Celsius and atmospheric pressure.

Atomic force microscopy showed that the gallium phosphide layer had a root mean square roughness of about 0.52 nanometers, indicating high crystal quality with a low threading dislocation density. Pendellosung fringes observed from the double crystal omega two theta rocking curve at the silicon and gallium phosphide 004 reflections were consistent with smooth interfaces. The reciprocal space map of 224 defraction spots shows coherent gallium phosphide and silicon peaks, indicating that gallium phosphide is fully strained to the silicon substrate with good crystalline quality.

Forming an N plus layer by phosphorus diffusion before adding the gallium phosphide layer maintained the silicon bulk lifetime at up to millisecond levels. The gallium phosphide silicon lifetime was about 100 microseconds. Devices were constructed using either a layer of amorphous silicon, or a layer of molybdenum oxide.

The internal quantum efficiency of the molybdenum oxide device remained high at lower wavelengths than an amorphous silicon device did, but it also had a higher reflectance at lower wavelengths. Promising solar cell performance was observed for both devices. The amorphous silicon and molybdenum oxide devices had comparable efficiencies, open circuit voltages, and fill factors.

Overall, the molybdenum oxide layer performed better as a whole selective contact than the amorphous silicon layer did. While attempting this procedure, remember to keep the second wafer as clean as possible before loading into the MBE chamber, especially when depositing silicon nitride.

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Developing High Performance GaP/Si Heterojunction Solar Cells

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