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The rapid proliferation of Internet-of-Things (IoT) systems, wearable and implantable devices, and artificial intelligence (AI) technologies has increased demand for tightly integrated electronic and photonic platforms1,2. Optoelectronic components, including photonic integrated circuits (PICs), photodetectors, and pulse lasers, play a central role in such systems3,4. At nanometer scales, however, device behavior is governed by quantum confinement, charge transport, and coupled optical–electrical interactions5. Traditional design approaches rely on first-principles simulations and empirical parameter tuning6. As the number of possible material combinations, geometrical layouts, and connectivity patterns grows, exhaustive simulation-based screening becomes computationally impractical.
Machine learning (ML) techniques have been introduced to accelerate modeling and inverse design tasks7. Early implementations used artificial neural networks and Gaussian processes as surrogate predictors8. More recent deep learning (DL) architectures improved representation learning for photonic and nanoelectronic systems9. Despite these advances, existing DL-based approaches often suffer from limited interpretability, strong data dependency, and restricted generalization across materials and structural scales10. Many frameworks also separate physics constraints from learning, treating them as external validation rather than integrated components of the optimization process11.
In parallel, continued scaling of semiconductor devices has approached physical limits in conventional architectures12. Short-channel effects and electrostatic instability become increasingly significant below 100 nm13, motivating exploration of alternative materials and device structures. Two-dimensional (2D) materials, particularly transition metal dichalcogenides (TMDs), offer tunable bandgaps and atomic-scale thickness compatible with CMOS processes14. Monolayer materials such as MoS₂ and WS₂ exhibit favorable carrier mobility and electrostatic control15. Junctionless architectures further demonstrate that device performance is strongly dependent on structural topology as well as material composition16,17.
Graph Neural Networks (GNNs) provide a natural computational framework for modeling relational systems such as molecular lattices, nanostructures, and circuit topologies18,19,20,21. By operating on graph-structured representations rather than grid-based inputs, GNNs update node embeddings through message passing among neighboring components. In simplified form, node updates can be expressed as

where ϕnode and ψedge are learnable functions and
denotes a permutation-invariant aggregation operator. Such models have been applied to property prediction and topology inference in nanoelectronic systems22,23,24. Multi-scale approaches attempt to bridge atomic-scale simulations and device-level performance25, yet most implementations operate at a single structural resolution or assume fixed topologies. In quantum mechanical formulations, electronic structure is governed by the eigenvalue problem

where
is the Hamiltonian operator and Ek are energy eigenvalues. Density Functional Theory (DFT) provides tractable approximations but scales approximately as O(N3) with electron number, limiting direct application to large-scale topology exploration. As device complexity increases, repeated DFT evaluations become computationally prohibitive. These limitations highlight the need for differentiable approximations that retain physical structure while enabling scalable optimization26,27,28.
To address this methodological gap, nanoelectronic devices are formulated in this work as hierarchical graphs G=(V,E) spanning atomic, mesoscopic, and device scales29,30,31,32,33 Scale-specific GNN encoders extract structural embeddings, and cross-scale information exchange is implemented through attention-based fusion. Instead of repeatedly solving full DFT equations during optimization, a GNN-parameterized effective Hamiltonian
is introduced to approximate reference energy behavior while preserving Hermitian structure and locality constraints34,35,36,37,38,39,40,41.
Topology modification is formulated as a reinforcement learning (RL) problem⁴². For a state st ≡ Gt , actions modify graph connectivity under physical feasibility constraints. A composite reward function is defined as
rt = α⋅IQE(Gt) + β⋅Stability(Gt) - γ⋅Complexity(Gt),
where the coefficients α,β,γ regulate trade-offs among performance, robustness, and structural simplicity. Multi-objective optimization is handled through constrained formulations of the form.

Scalability to large systems is achieved using spectral graph coarsening and hierarchical aggregation, enabling efficient learning and inference on graphs containing up to millions of nodes without compromising structural fidelity. Spectral graph coarsening reduces computational complexity by clustering nodes based on eigenstructure similarity, preserving key topological and spectral properties while significantly decreasing graph size. Hierarchical aggregation further organizes the reduced graph into multi-resolution representations, allowing the model to process local and global dependencies in a staged manner. This multi-level strategy lowers memory consumption, accelerates message passing operations, and maintains predictive accuracy, thereby ensuring that the framework remains computationally tractable for large-scale nanoelectronic and optoelectronic device modeling43,44,45,46,47,48,49,50,51.
The objective of this study is therefore to implement and evaluate a reproducible, multi-scale, physics-informed GNN framework for constrained nanoelectronic device design The overall workflow of the AI-driven multi-scale nanoelectronic design framework integrates dataset preparation, hierarchical graph construction, quantum-informed modeling, reinforcement learning–based topology evolution, and physics-based validation (Figure 1). The following sections describe the computational protocol, training configuration, and validation procedures.