A Resolution-Adaptive Hardware Architecture for Real-Time Sobel Edge Detection, Achieving Sub-Linear Resource Scaling

Summary

This work presents an FPGA-based implementation of the Sobel edge detection algorithm on the Ultra96-V2 heterogeneous platform, evaluating resource utilization, power, and speed across image resolutions ranging from 256 × 256 to 2560 × 1440. The proposed architecture demonstrates sub-linear resource scaling for real-time image processing applications.

Abstract

Edge detection is a key area within computer vision, and it has become an integral part of various application areas. Edge detection enables the identification of edges, which are critical features in images and represent important attributes that help in extracting key and distinguishing information from the images. The hardware implementation of edge detection must be fast, should use minimal resources, consume less power, and must be adaptable to different image resolutions. This paper implements Sobel edge detection for adaptive image resolution, ranging from a low-resolution image to full high-definition, and uses a modern heterogeneous Field Programmable Gate Array (FPGA) platform, the Ultra96-V2. The results reveal that only 5% of the FPGA on-board resources, including the Look up Tables (LUTs), Flip Flops (FF), Digital Signal Processor (DSP), and Block Memory (BRAM), are utilized for low resolution images, while approximately 23% of the onboard resources are consumed for high resolution images. This demonstrates that the increase in resource utilization when transitioning from low resolution to high resolution images is less than 20%. Additionally, the power dissipation is approximately 2 W for the highest resolution, and the maximum operational frequency is recorded at 136 MHz for high resolution and 166 MHz for low resolution images, showing only 18% decrease in the frequency. The proposed architecture achieves sub-linear resource scaling, with less than 20% increase in resource utilization and less than 20% reduction in speed and power when handling a 56-fold increase in pixel count, leveraging the advantages of modern heterogeneous FPGA architecture. Consequently, the adaptive resolution capability combined with low resource scaling makes the proposed design particularly suitable for real-time edge detection applications demanding high-quality image processing.

Introduction

Edge Detection has become a crucial element in nearly all computer vision techniques used across various application domains today¹. Edge detection is a feature extraction stage and is responsible for retrieving informative and distinctive details from images, which can be applied in a wide range of scenarios². Edges within an image signify regions where there is a sudden change in intensity; therefore, they offer important and distinctive information about that image. This process facilitates the elimination of unnecessary and irrelevant details, preserving only the crucial and unique elements that can be further processed for the specific application.

The importance of edge detection is highlighted by its application in various tasks, including image segmentation, object detection and recognition, feature extraction, image enhancement, object identification, medical imaging, surveillance, industrial automation, autonomous driving, augmented reality, and robotics^2,3,4,5,6, as shown in Figure 1.

Multiple methods for edge detection exist, including Sobel, Prewitt, Roberts, Canny, and others. Among these techniques, Sobel edge detection stands out due to its straightforward application, minimal implementation complexity, and high precision in detecting edges^3,4,5,6. The image's gradients are determined by the Sobel Edge algorithm in both horizontal and vertical directions using the kernels Gx and Gy respectively as shown below^2,4.

Gx highlights the edges in the × direction, and Gy highlights edges in the y direction^12,13. When combined together they completely define all the edges in an image⁶. The convolution with the kernel process and the sliding window are used to apply the Sobel edge detection to an image. One by one, a window measuring, say, 3 by 3 pixels is taken out of the picture, and this window is convolved with the filter matrix to obtain the new value of the center pixel. The entire image is processed in this manner again. Two such kernels are used in Sobel edge detection: one for extracting edges in the x direction and another for the y direction. To obtain all the edges, these two results are then combined. Sobel edge detection produces accurate and reliable results, which can be further enhanced with some pre-processing^4,5,15. The complete Sobel edge detection is interpreted in Figure 2.

Although all the reported literature has significant contributions in the field of edge detection, all the major reported research has worked on low image resolutions, whereas the work presented in this paper works on different image resolutions, varying from low-resolution images (256 × 256) to full high-definition (HD) image resolution (2560 × 1440). Consequently, investigating the hardware implementation of the Sobel edge detection algorithm for different image resolutions is crucial to understanding the efficiency of the implementation when it is subjected to real-time scenarios with varied image resolutions. The Field Programmable Gate Array (FPGA) has been acknowledged as an appropriate platform for hardware implementations, due to its suitability for rapid prototype development and advantages like re-configurability, which enables easy design modifications without the need to change the entire hardware configuration^{6,7,8,9,10,11,12,13}. Furthermore, FPGAs offer the potential for parallel processing and pipelining; once the performance metrics are optimized and the platform validated, the design can progress towards the actual production of Application Specific Integrated Circuits (ASICs)^14,15. Another important feature of FPGA is their reconfigurability, which enables designers to make modifications to the product's design at any time without the need to replace any hardware. Reprogramming the chip is all that is necessary, and it takes very little time or effort, provided the designer is well versed with hardware description languages like VHDL/Verilog^4,6,13,16,17. For the FPGA implementation analysis, the major parameters considered are speed (maximum frequency), resource utilization, and power efficiency. Table 1, which depicts the increasing amount of literature published in the domain of FPGA and it shows how FPGA publications have evolved over the period from 2006 to 2024. It clearly explains that the FPGA research domain has now shifted to real-time applications, augmented reality, edge computing, and other high-end applications^{13,14,15,16,17,18,19,20,21,22,23}.

Table 2 highlights the work done in the existing literature related to Sobel edge detection implementation on FPGA since 2020–2025. Table 2 mentions the FPGA board used, algorithms implemented, Design methodology, findings, metrics, application area, and the challenges of each referred article.

The authors⁴ have recommended using the 8-direction Sobel Edge method to increase edge detection accuracy, however, they reported higher resource consumption for the proposed methodology. Navinkumar et. al. utilize a technique to reduce the complex mathematical operations of multiplication and square root that are involved in the traditional Sobel edge detection, and save the onboard resources and improve the speed⁹. The authors¹⁷ documented about using the Sobel Edge Detection Algorithm to identify lanes in Advanced Driver Assistance Systems. Their goal was to speed up detection while cutting down on processing time. Overall, usage of edge detection was suggested as a reliable method for region of interest extraction in the future, which may be very helpful in a variety of applications where the needed area of an image needs to be extracted while ignoring any other unnecessary information. The challenges reported collectively included, higher resource and memory utilization, sensitivity to noise, high computational cost and limited scalability for higher resolution images^{4,5,6,11,12,13,21,22,23}.

In this work, the traditional Sobel edge detection algorithm implementation is done on the Ultra96-V2 FPGA board, for different image resolutions ranging from low resolution of 256 × 256 to full high-definition resolution of 2560 × 1440. Ultra96-V2 is a board that combines the FPGA programmability capabilities with the powerful Arm processing (Cortex-A53/R5) for high-performance applications. This board was first released in 2018, and it utilizes 16 nm FinFET technology node¹⁸.

To ensure reproducibility, the entire implementation was carried out using a standard toolchain consisting of the Vivado HLS 2019.2 for High-Level Synthesis (HLS) and Vivado 2019.2 for place-and-route, as well as the PYNQ image released by Ultra96-V2 resources. The HLS code was utilized to derive the Sobel edge detection IP (Intellectual Property), which was exported and integrated into the Vivado design suite. The IP was implemented on the PL (Programmable Logic) part, and the PS (Processing System) part of the FPGA was responsible for data transfer and control mechanisms. The interfacing of PS with the PL was done through the AXI protocol. All reported metrics—frequency, resource utilization, and power—are taken from post-implementation reports, not HLS estimates. The implementation settings remained consistent, and only the image resolutions were changed throughout the experiments.

Significant achievements of this work are in terms of low power consumption, low resource utilization, and high speed. The results indicate less than 20% of the onboard resource utilizations (18% Look Up Tables (LUTs), 11% Flip Flops (FF), 3% memory, and 10% DSP) for the high-resolution images, indicating huge availability for integrating much more processing on these images, which is expected in any computer vision system, as edge detection is only an intermediate step. Also, the power dissipation is nearly 2 W, and the maximum operating frequency is reported as 144 MHz. The results depict that scaling the image sizes by almost 56 times increases the resource utilization by almost 20% only. The speed and power dissipation are also degraded by almost 20% only. This analysis significantly investigates the algorithm from a different perspective, which has not been reported in other previous literature, and hence indicates that the implementation is well-suited for real-time applications with no need to limit the images to small sizes/less resolution, which definitely degrades the amount of information which is required in subsequent stages after edge detection.

The novelty of this work is not in the algorithm itself, but it focuses on assessing the performance of the traditional Sobel edge detection algorithm across various image resolutions on modern heterogeneous FPGA architectures, leveraging the advantages of HLS-based implementation techniques. The key contributions of this paper are primarily in the application of a hybrid methodology implemented on an FPGA, effectively distributing the workload between the PS and PL sections of the architecture to allow the design to effortlessly adjust to different resolutions. Another contribution involves experimenting to assess how resource scaling varies with changes in image resolutions, which helps in understanding performance across different setups and for diverse applications.

Protocol

1. Sobel edge detection implementation on the HLS tool

1. Open the Vivado HLS 2019.2 tool and create a project. Select the FPGA board as Ultra96-V2.
2. Write the high-level language code using the C++ language for Sobel edge detection with the image size parameter generalized and not fixed.
   NOTE: The image width and height are not fixed and written as a general parameter in the code so that they can be easily changed while varying the image resolution without the need to change at multiple locations.
3. Write the test bench code for the Sobel edge detection algorithm in C++.
   NOTE: The test bench is written to provide the input images on which the code is tested.
4. Click on “run C simulation” to simulate the code to check the functional correctness. Give an input image to the test bench and then check the generated output, which should be an image with edges.
5. Click on “run C synthesis” to synthesize the HLS code and export the IP for Sobel edge detection.
   NOTE: The synthesis process basically maps the coded design to hardware components and makes the design compatible and ready for hardware implementation.
6. Check the timing and resource utilization reports generated by the tool and ensure that the estimated time is not more than the targeted time.
   NOTE: All these results from the HLS platform are just an estimate, and the actual parameters are calculated only when the design is implemented on an FPGA.
7. Click on “export IP” to export the IP of the Sobel edge detection procedure.
   NOTE: This IP is used in the next step while designing the block diagram for FPGA implementation on the Vivado tool.

2. Implementation of Sobel Edge detection on FPGA Platform, Ultra96-V2 using extracted HLS IP

1. Open the Vivado Design Tool and create a new project. Select the target board as Ultra96-V2 and click on “Create a new block design”.
2. Import the Sobel edge IP just exported from the HLS tool. Add the other necessary blocks for completing the interfacing between the PS and the PL part.
   NOTE: The block diagram uses other important IP blocks as well, like the Zynq Ultrascale IP, the Smart Connect, and the processor reset, etc for establishing the interface between PS and PL using the Advanced eXtensible Interface (AXI) protocol.
3. Click on the “validate design” to validate the block design. Ensure that there are no design errors reported by the tool. If there are errors, follow the instructions for correction and validate again.
   NOTE: This step ensures that there are no missing connections in the block diagram, but it does not verify the functional correctness of the block design.
4. Click on “create the HDL wrapper” to get a generalized HDL code for the block design.
5. Click on “run synthesis” to synthesize the design to check for any reported errors. If no errors are found, then the tool reports successful synthesis. After successfully synthesizing, access the synthesis reports of timing to check for any timing violations.
6. To check for timing violations, ensure that none of the timing is reported in red text, as this signifies that the utilized time is more than the target assigned and hence signifies violations.
7. Click on “run implementation”, to implement the design and assess the timing, power, and resource utilization report.
8. Generate the “.bit” file to program the FPGA board.
   NOTE: The block diagram for Sobel edge detection on Ultra96-V2 is shown in Figure 3. As already stated, the block diagram is basically required to establish an interface between the PS and the PL part of the FPGA board.

3. Programming the FPGA board

1. To prepare the SD card, download the PYNQ image file (.img) for the Ultra96-V2 board¹⁶ and install the downloaded file on the SD card.
2. Power on the board in the SD card boot mode by selecting the switch positions as per the Ultra96-V2 reference manual16.
3. Visit the URL, http://192.168.3.1, and type in the username and password, both as “xilinx” when prompted.
   NOTE: It is preferred to use the Google Chrome browser to avoid any technical mismatches.
4. Access the Jupyter platform and write Python code for the PS part to read the input images or videos and send the read image to the PL part for processing.
5. Write code for the task of writing back the processed images from PL to PS and displaying the result.
   NOTE: For displaying the results on Ultra96-V2, the PYNQ platform is used, which makes it much easier to display the output images simply through the usage of the Python codes and the OpenCV libraries.
   Figure 4 shows the steps for the Ultra96-V2 approach as demonstrated in this section and obtained outputs.

Results

This section discusses the results obtained in the design of Sobel edge detection on Ultra96-V2. Figure 5 below shows the input and the output images obtained through HLS simulation. The images used are the standard images of size 512 × 512. These results showcase that the HLS code written for Sobel edge detection is functionally correct. The edges must be clearly visible in the resultant images.

Table 3 shows the synthesis reports and the generated parameters of timing and resource utilization on the Ultra96-V2 with the FPGA part as xczu3eg-sbva484-1-e. The report consists of information related to timing that illustrates whether the design meets the timing constraints as specified by the user. As per the timing summary, the estimated time of 8.544 ns is less than the target time of 10 ns, which clearly suggests that the design is meeting the user constraints.

HLS tools also generate an estimated resource utilization, which provides the designer with an estimate of the possible usage of the onboard resources. The actual utilization parameters can only be generated after actual hardware realization. Although there are huge and different categories of resources on an FPGA, the most used hardware are LUTs (Look up Tables), FFs (Flip Flops), DSP Slices (Digital Signal Processing Slices), and memory.

Table 3 also shows the actual timing and resource utilization when Sobel edge detection is developed on the Ultra96-V2 for high-resolution images. The timing analysis shows that the worst negative slack is 3.102 ns, which signifies that there is enough time for processing, and hence the clock speed of 144 MHz is achieved. The achieved operating frequency of 144 MHz at 1920 × 1080 resolution corresponds to a throughput of approximately 299 MP/s, which exceeds the 62 MP/s required for real-time full HD video processing at 30 fps. To understand the resource scaling and effect on parameters while moving from low resolution to high resolution images, the table is reported through the experimental results that involve the same steps repeated for different resolutions.

Table 4 mentions the image size and hence total pixels, and then the operating frequency, power, and resource utilizations in terms of LUTs, FFs, BRAM, and DSP. It can be clearly indicated that while transitioning from the smallest considered resolution of 256 × 256 to the highest of 2560 × 1440, which involves almost a 56-fold increase in the pixel count, the parameters are changed only by 20%. This clearly indicated sub-linear resource scaling wherein the data to be processed is increasing by many folds, but the degradation in the performance metrics is very minimal, making it suitable for real-time deployment.

The results presented in Table 4 clearly demonstrate that the application of Sobel edge detection on the Ultra96-V2 offers significant advantages for tasks requiring adaptable resolutions, as the performance metrics remain optimized and do not exhibit considerable changes when updating the image size from low to high resolution. This success is attributed to the hybrid implementation approach that avoids overloading the FPGA logic with image data, enabling the board's processor to manage the substantial image workload. The processor simply relays the image data to the FPGA logic component, with any increase in resource scaling or reduction in the maximum frequency being solely a result of the large data volume that requires more handling. Thus, it can be stated that the approach followed in this paper achieves sublinear resource scaling even though the image pixels increase by almost 56-fold.

The implemented work is also compared with the existing designs to understand the comparison between the performance metrics, such as image resolution, clock frequency, power consumption, and resource utilization. Table 5 depicts the comparison with the latest literature.

As clearly illustrated by Table 5, the work implemented in this paper has appropriate performance metrics, but the existing solutions of previous reported implementations^9,10have better parameters. But when overall comparison is done, it can be noted that both previous work^9,10have worked on low image resolution and on legacy FPGA platforms, whereas the results depicted in this paper are according to the adaptive image resolutions, where the image size considered ranges from the lowest resolution of 256 × 256 to high-definition resolution of up to 2560 × 1440. The results indicate that the implemented Sobel edge detection approach that utilizes the capabilities of both the processor and the logic part of the heterogeneous FPGA board, Ultra96-V2, proves to be useful in achieving sub-linear resource scaling as the pixel count increases almost 56 times, but the resource utilization increases only by 20%, and the degradation in power and speed is also less than 20%. For the lowest resolution, only 5% of resources are used, and the maximum utilization is only 23%, leaving huge availability for further processing. Thus, it can be clearly stated that because of the difference in the image resolutions, it is difficult to compare, but if the design implemented in this work is analyzed, then the clock frequency is 136 MHz, the power consumption is also 2 W, and the resource utilization is less than 23% of the overall on-board resources. It is important to state that the implementations reported in previous works^9,10demonstrate superior individual performance metrics. However, it is important to note that both works evaluate their designs at a single fixed image resolution, whereas the proposed work is evaluated across a wide range of resolutions from 256 × 256 to 2560 × 1440. The design objectives are therefore fundamentally different as the work^9,10optimize for peak performance at one resolution, while the proposed architecture prioritizes adaptability and sub-linear resource scaling across multiple resolutions. This makes the implemented design suitable for applications that require edge detection.

It can thus be stated that, in this work, sub-linear resource scaling is defined as the condition where the percentage increase in resource utilization is significantly lower than the percentage increase in pixel count. When the resolution increases from 256 × 256 to 2560 × 1440, the pixel count increases by approximately 5600%, whereas the on-board resource utilization increases by less than 20%. This disproportionately low resource growth rate, directly resulting from the PS-PL heterogeneous partitioning strategy, confirms the sub-linear scaling behavior of the proposed architecture. While the proposed implementation demonstrates sub-linear resource scaling across the tested resolution range, certain limitations should be noted for accurate interpretation of the results. The operating frequency decreases by 18% from low to high resolution, and extrapolation beyond 2560 × 1440 may require architectural adjustment to maintain timing closure. Additionally, since image data transfer is managed by the ARM processor, the PS-side transfer overhead grows linearly with pixel count and may limit throughput in continuous high-resolution video streaming applications beyond what the PL-side metrics alone suggest.

Figure 1: Various application areas of edge detection. Illustration of representative application areas in which edge detection is commonly used, including computer vision, medical imaging, surveillance, robotics, and industrial automation. Please click here to view a larger version of this figure.

Figure 2: Description of steps in Sobel edge detection algorithm. Workflow illustrating the Sobel edge detection process, including extraction of a 3 × 3 image window, convolution with horizontal and vertical Sobel kernels, and generation of the edge-detected output image. Please click here to view a larger version of this figure.

Figure 3: Implemented block diagram for Sobel edge detection on Ultra96-V2 FPGA board using interfacing between the PS (processing system) and PL (programmable logic) part. Block diagram showing the hardware architecture and interconnection of the processing system (PS), programmable logic (PL), and supporting IP cores used for the FPGA implementation. Please click here to view a larger version of this figure.

Figure 4: Steps for programming the Ultra96-V2 board for Sobel edge detection using the PYNQ platform and the result of Sobel edge detection on an input image. Workflow showing the programming procedure for the Ultra96-V2 board using the PYNQ platform and a representative output image obtained after FPGA implementation. Please click here to view a larger version of this figure.

Figure 5: Simulation results for Sobel edge detection on different standard images using Vivado HLS (2019.2). Representative input images and their corresponding edge-detected outputs obtained during functional simulation of the Sobel edge detection algorithm using Vivado HLS 2019.2. Please click here to view a larger version of this figure.

Table 1: Evolution of FPGA applications in computer vision research (2006–2024). Summary of representative FPGA-based computer vision applications reported between 2006 and 2024. Please click here to download this Table.

Table 2: Related literature for the implementation of edge detection algorithms on FPGA (2020-2025). Comparison of recent FPGA-based edge detection implementations, including platform, methodology, and reported performance metrics. Please click here to download this Table.

Table 3: Sobel edge detection implementation on FPGA: estimated parameters and actual parameters. Estimated HLS synthesis results and corresponding post-implementation timing and resource utilization obtained for the FPGA implementation. Please click here to download this Table.

Table 4: Resource utilization and performance metrics of the implemented Sobel edge detection algorithm on different image resolutions. Performance metrics, operating frequency, power consumption, and FPGA resource utilization of the proposed implementation across different image resolutions. Please click here to download this Table.

Table 5: Comparison of implemented and existing Sobel edge detection on FPGA. Comparison of the proposed FPGA implementation with previously reported Sobel edge detection implementations using representative performance metrics. Please click here to download this Table.

Discussion

This paper focuses on executing the Sobel edge detection algorithm, which is an essential component in various applications across multiple fields of computer vision and image processing^2,3,4,5,6. The Sobel edge detection implementation is carried out using the Vivado HLS tool, enabling coding in higher-level languages instead of relying on hardware description languages. The Vivado HLS code is run on the Ultra96-V2 board. The post-implementation results indicate that the implemented design supports high-resolution images and runs at a frequency of 136 MHz with 2 W power consumption and less than 20% of the total on-board resources. Also, the results showcased that the approach is suitable for adaptive resolution of images, as different applications may demand the use of varied image sizes, and edge detection is usually an intermediate step^2,3,4,5,6, which is done very frequently in complex design pipelines. Thus, it can be stated that the designed system can be deployed in real-time applications that require edge detection. The huge availability of resources suggests that various other processing steps can be incorporated into the developed system^{6,7,8,9,10,11,12,13,14,15}.

Successful implementation of the Sobel edge detector on the Ultra96-V2 board requires careful attention to several practical aspects. The PYNQ framework considerably simplifies PS–PL interaction by enabling hardware control through Python libraries, thereby reducing software development effort. However, the correct PYNQ image must be downloaded from the official source, and the SD card must be configured properly before deployment. Functional verification of the HLS design using comprehensive test benches is essential prior to IP export, as early validation helps identify algorithmic and interface errors before hardware implementation. During FPGA implementations, the block diagram design also requires huge designer attention, as it is advised to properly understand the architecture of the FPGA hardware under consideration and hence select the proper blocks and make the connections. It is not advised to automate the connections completely, as that could lead to missing connections or connections not suitable for the design to be followed. At this stage of PS–PL interface, errors such as incorrect AXI address mapping, clock-domain mismatches, or improperly configured DMA transfers may prevent successful communication between the processor and programmable logic. These issues can be identified using Vivado's design validation tools and resolved by verifying address assignments, clock configurations, interrupt connections, and DMA settings before bitstream generation. During FPGA implementation, timing violations may occur because of long combinational paths or inadequate pipelining. Increasing pipeline stages, optimizing loop structures, or relaxing timing constraints where appropriate can help achieve timing closure.

While this work validates the proposed PS-PL partitioning architecture specifically for Sobel edge detection, the architectural approach is inherently generalizable. Any algorithm that can be expressed as a sliding window convolution—including Prewitt, Roberts, Laplacian of Gaussian, or Canny's gradient stage can be implemented with a similar approach, with changes in the HLS design mainly^3,4,5,6. There are certain limitations of the proposed work. One of the limitations is the delay because of data transfer between the PS and the PL part of the FPGA, which affects the entire execution time of the algorithm. Furthermore, the sub-linear scaling finding is particular to the Ultra96-V2 heterogeneous architecture¹⁶ and might not directly apply to homogeneous FPGA platforms lacking a dedicated processor core.

The future scope involves further improvement of the design with certain optimizations that may improve the speed and reduce the power further. Also, adapting the implementation into real-time scenarios is another potential aspect for consideration in the future.

Materials

List of materials used in this article

Name	Company	Catalog Number	Comments
Ultra96-V2 FPGA Board	Xilinx	Introduced in 2018	Hardware Implementation Platform used for implementing the pedestrian detection algorithm
Vivado HLS	AMD	2019.2	High Level Synthesis Tool used for high level programming of the pedestrian detection code in the paper to export the Intellectual Property (IP)
Vivado	AMD	2019.2	FPGA Programming tool used for programming the Ultra 96 v2 FPGA board with the Sobel edge detection algorithm