29.1
Seri R-L Devre Geçişleri
Seri direnç-endüktör (R-L) devresinde, zaman periyodunun başlangıcında anahtarın kapatılması, yüksüz bir senkron makinenin üç fazının da kısa devre ol…
Bir seri R-L devresi düşünün.
Anahtar sıfıra eşit bir zamanda kapandığında, yüksüz bir senkron makinede üç fazlı kısa devreyi taklit eder.
Sıfır arıza empedansı veya cıvatalı bir arıza ve sıfır başlangıç akımı verildiğinde, kaynak açısı ilk kaynak voltajını belirler.
Bu devrenin KVL denklemi, toplam asimetrik arıza akımını ve iki bileşenini verir.
Simetrik veya kararlı durum arıza akımı olarak da adlandırılan AC arıza akımı, bir sinüzoiddir.
DC ofset akımı, endüktans-direnç oranı olarak bir zaman sabiti ile üstel olarak azalır.
Büyüklüğü kaynak açısına göre değişir ve kaynak açısı teta artı pi'ye iki üzeri eşit olduğunda zirveye ulaşır.
En büyük arıza akımı belirli bir kaynak açısında meydana gelir.
Maksimum dc ofsetli rms asimetrik arıza akımı daha sonra döngü ve frekans cinsinden zaman sabiti ve zaman ikame edilerek hesaplanır ve basitleştirilir.
Bu akım, rms AC arıza akımı çarpı bir asimetri faktörüne eşittir ve tau arttıkça rms akımı azalır.
Direnç oranlarına daha yüksek reaktans, daha yüksek rms akımı değerleri verir.
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Q1: What are the two main components of asymmetrical fault current in an R-L circuit?
Asymmetrical fault current consists of two components: the AC fault current (also called symmetrical or steady-state fault current), which follows a sinusoidal pattern, and the DC offset current, which decays exponentially over time. The DC offset's magnitude depends on the source angle and peaks at a specific phase angle. Together, these components determine the total fault current response when a switch closes in a series R-L circuit.
Q2: How does the DC offset current decay in a series R-L circuit?
The DC offset current decays exponentially with a time constant defined by the inductance-to-resistance ratio (L/R). The rate of decay depends directly on this ratio; higher inductance relative to resistance results in slower decay. The magnitude of the DC offset varies with the source angle, peaking when the source angle equals theta plus pi over two, which determines the maximum initial offset current.
Q3: What does a series R-L circuit model when the switch closes at time zero?
When the switch closes at time zero in a series R-L circuit with zero fault impedance and zero initial current, it simulates a three phase short circuit in an unloaded synchronous machine. The source voltage phase angle determines the initial voltage at the moment of switching. This setup allows engineers to analyze fault conditions and understand how circuit parameters affect the resulting fault current behavior.
Q4: How is the RMS asymmetrical fault current calculated?
The RMS asymmetrical fault current is calculated by multiplying the RMS AC fault current by an asymmetry factor that reflects the influence of the DC offset current. The calculation expresses the time constant and time in terms of cycles and frequency. As the time constant increases, the RMS current decreases, demonstrating that higher inductance-to-resistance ratios yield higher RMS current values.
Q5: What role does Kirchhoff's Voltage Law play in fault current analysis?
Kirchhoff's Voltage Law (KVL) is applied to the series R-L circuit to determine the total asymmetrical fault current and its two components. By analyzing the voltage equation across the resistor and inductor, engineers can derive expressions for both the AC and DC offset currents. This fundamental circuit analysis technique enables prediction of fault current magnitude and behavior under different source angle conditions.
Q6: Why does the maximum fault current occur at a specific source angle?
The magnitude of the DC offset current, which significantly contributes to the total asymmetrical fault current, varies with the source angle. The DC offset peaks when the source angle equals theta plus pi over two, resulting in the largest total fault current at this specific phase angle. Understanding this relationship helps engineers predict worst-case fault scenarios and design protective systems accordingly.
Q7: How does the reactance-to-resistance ratio affect RMS fault current?
Higher reactance-to-resistance ratios result in higher RMS asymmetrical fault current values. This ratio directly influences the time constant (L/R), which governs the decay rate of the DC offset component. Since the asymmetry factor depends on this time constant, circuits with greater inductance relative to resistance produce larger and more persistent fault currents, requiring more robust protective equipment.