Name: Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping (Video) | JoVE Journal
Uploaded: 2015-06-03T15:00:00.000+00:00
Duration: 14 min 58 s
Description: Learn to fabricate silicon metal-oxide-semiconductor quantum dots and operate them as single-electron pumps using multi-layer gate techniques. This method enables precise control of electron transfer for quantum electrical metrology applications.

ai_agent_IP

ai_agent

maintenance

instantTrialDurationMinutes

isBiopharma

enableNewMyJoveSectionDesign

educationFeatures

seoMetaApi

ai_copilot_institution_blacklist

ai_chat_institution_blacklist

freeAccessWindow

ssoRoleCapture

scheduledMaintenanceBanner

joveLabsFeatures

disable_autoplay_for_bots

extended_trial_duration

5 minutes

We thank K. Y. Tan, P. See and G. C. Tettamanzi for useful discussions. We acknowledge financial support from the Australian Research Council (Grant No. DP120104710), the Academy of Finland (Grant No. 251748, 135794, 272806) and support from the Australian National Fabrication Facility for device fabrication. A.R. acknowledges financial support from the University of New South Wales Early Career Researcher Grant scheme. The provision of facilities and technical support by Aalto University at Micronova Nanofabrication Centre is also acknowledged.

Note: This protocol describes the procedures used to fabricate, package and test single-electron pumps based on silicon MOS QD technology. The steps discussed in sub-sections 1 and 2 are carried out in an ISO5 cleanroom, while those of section 3 are performed in ISO6 laboratories. Ambient conditions are continuously controlled. Nominal values for temperature and humidity are set at 20 &#177; 1 &#176;C and 55% &#177; 5%, respectively.
1. Microfabrication
<ol>
	<li>Field Oxide
	<ol>
		<li>Clean the wafer by immersion in the following: piranha etch (10 min), deionized (DI) water (10 min), RCA-2 solution (DI water 175 ml, HCl 30 ml, H2O2 30 ml at 100 &#176;C for 10 min), deionized water (5 min), hydrofluoric (HF) acid diluted in water 10:1 (10 sec), DI water (10 min). Use protective garments when handling HF (i.e., goggles, PVC apron, and PVC gloves). Proceed in the stated order.</li>
		<li>Place the wafer in oxidation furnace at 900 &#176;C and oxidize in steps as follows: dry O2 (10 min), wet O2 (40 min), dry O2 (10 min), N2 (15 min).</li>
	</ol>
	</li>
	<li>Ohmic Contacts
	<ol>
		<li>Carry out photolithography and etch oxide.
		<ol>
			<li>Deposit a few-nm-thick layer of adhesion promoter hexamethyldisilazane (HMDS) onto the wafer surface as follows: pre-bake on a hotplate at 110 &#176;C for 1 min, pour ~50 ml of HMDS in a glass beaker, place the beaker and the wafer in the vacuum chamber, evacuate and wait for 2 min.</li>
			<li>Spin a 2&#8211;4-&#956;m-thick layer of photoresist on both back and front sides of the wafer (3,000&#8211;5,000 rpm, 25&#8211;40 sec depending on desired thickness).</li>
			<li>Expose to ultra-violet light in mask aligner (10 mW/cm2 for 4&#8211;10 sec according to resist thickness). Post-bake on a hotplate at 110 &#176;C for 1 min.</li>
			<li>Develop for 1&#8211;2 min, then rinse in deionized water.</li>
			<li>Perform O2 plasma etch for 20 min (pressure = 340 mTorr; incident power = 50 W; reflected power &#60; 1 W).</li>
			<li>Etch oxide in buffered HF acid solution (15:1, 4&#8211;5 min, etch rate &#8776; 20 nm/min at 30 &#176;C). Rinse in deionized water (5 min). Blow dry with N2.</li>
		</ol>
		</li>
		<li>Remove photoresist by immersion in acetone. Rinse in isopropanol (IPA), then blow dry with N2.</li>
		<li>Place wafer in furnace at 1,000 &#176;C with phosphorus source (N2 flow for 30&#8211;45 min depending on desired doping density).</li>
		<li>Remove contaminated oxide layer with HF acid diluted in water (10:1, 3&#8211;4 min, etch rate &#8776; 40 nm/min at 30 &#176;C), rinse in deionized water (10 min).</li>
		<li>Oxidize as in 1.1.2.</li>
	</ol>
	</li>
	<li>Gate Oxide
	<ol>
		<li>Repeat steps 1.2.1 and 1.2.2.</li>
		<li>Place wafer in dedicated furnace at 800 &#176;C and oxidize in steps as follows: dry O2 (10 min), dichloroethylene+O2 (20 min), dry O2 (10&#8211;30 min depending on desired oxide thickness), N2 (15 min).</li>
	</ol>
	</li>
	<li>Ohmic Contacts Metallization
	<ol>
		<li>Repeat step 1.2.1.</li>
		<li>Place wafer in electron-beam evaporator. Evaporate 100 nm of aluminum at 0.2&#8211;0.5 nm/sec and 5 x 10-6 Torr.</li>
		<li>Soak the wafer in N-methyl-2-pyrrolidone (NMP) on hotplate at 80 &#176;C for 1 hr to lift off the metal. Use ultrasonic agitation if needed. Rinse in IPA for 2 min. Blow dry with N2.</li>
		<li>Anneal in forming gas at 400 &#176;C for at least 15 min.</li>
	</ol>
	</li>
</ol>
2. Nanofabrication
<ol>
	<li>Wafer Dicing
	<ol>
		<li>Spin any resist onto the wafer to act as protective coating (type of polymer and spinning parameters are irrelevant at this stage).</li>
		<li>Use diamond tip dicer to cut the wafer into individual chips of ~10 x 2 mm2.</li>
	</ol>
	</li>
	<li>Cleaning
	<ol>
		<li>Soak in NMP for 1 hr on hotplate at 80 &#176;C, then rinse in IPA for 2 min. Blow dry with N2.</li>
		<li>Perform O2 plasma etch for 5 min (incident power = 50 W; reflected power &#60; 1 W).</li>
		<li>Spin clean with acetone and IPA (7,500 rpm, 30 sec)</li>
	</ol>
	</li>
	<li>Alignment markers patterning
	<ol>
		<li>Spin polymethyl methacrylate (PMMA 950k) A4 resist (5,000&#8211;7,500 rpm, 30 sec depending on desired thickness). Typical working thickness &#8776; 150&#8211;200 nm. Bake the resist on a hotplate at 180 &#176;C for 90 sec.</li>
		<li>Carry out e-beam lithography. Use the following write conditions: beam energy = 30 keV, beam current &#8776; 30 pA, area dose &#8776; 500&#8211;650 &#181;C/cm2 depending on markers size and resist thickness.</li>
		<li>Develop the resist in a solution of methyl isobutyl ketone and IPA (1:3) for 40&#8211;60 sec, then rinse in IPA for 20 sec. Blow dry with N2 gun.</li>
		<li>Place the chip in electron-beam evaporator. Evaporate 15 nm of Ti and 65 nm of Pt at 0.2&#8211;0.4 nm/sec and 5 x 10-6 Torr.</li>
		<li>Lift off the metal as in step 1.4.3.</li>
		<li>Clean chip as in steps 2.2.2&#8211;2.2.3.</li>
	</ol>
	</li>
	<li>Gate patterning
	<ol>
		<li>Spin resist as in 2.3.1.</li>
		<li>Carry out e-beam lithography. Use the following write conditions for high resolution features: beam energy = 30 keV, beam current &#8776; 30 pA, area dose &#8776; 500&#8211;700 &#181;C/cm2. Write conditions for low resolution features: beam energy = 15 keV, beam current &#8776; 10 nA, area dose &#8776; 400&#8211;600 &#181;C/cm2.</li>
		<li>Develop the resist as in 2.3.3.</li>
		<li>Place the chip in thermal evaporator. Evaporate Al at 0.1&#8211;0.4 nm/sec and 1&#8211;9 x 10-6 mbar. Target thickness varies according to layer number, as shown in Figure 2B (25&#8211;35 nm for Layer 1, 45&#8211;65 nm for Layer 2, 75&#8211;90 nm for Layer 3).</li>
		<li>Lift off the metal as in step 1.4.3.</li>
		<li>Perform Al oxidation on a hotplate at 150 &#176;C for 5&#8211;10 min.</li>
		<li>Clean chip as in step 2.2.3.</li>
		<li>Repeat steps 2.4.1&#8211;2.4.7 twice to realize the 3-layer gate stack.</li>
	</ol>
	</li>
</ol>
3. Device Packaging
<ol>
	<li>Dice chip as in step 2.1</li>
	<li>Rinse the resulting smaller chips in acetone and IPA for 2 min.</li>
	<li>Glue an individual piece to a printed circuit board (PCB) with PMMA A5. Wait 2 min for it to dry. Alternatively, to enhance thermalization, use silver epoxy.</li>
	<li>Load the PCB onto a wedge bonder and proceed with wiring.</li>
</ol>
4. Device Integrity Tests
<ol>
	<li>Mount the PCB containing the wired device onto a dip probe.</li>
	<li>Wire the electrical lines of the PCB to those of the dip probe.</li>
	<li>Insert the probe into a vessel containing liquid helium. Proceed slowly to avoid excessive helium boil-off.</li>
	<li>For each device gate, connect the corresponding room-temperature electrode of the probe to a source-measure unit, while keeping the other gates grounded. Set the compliance current to few nA. Sweep the voltage from zero to 1.5V in steps of 0.1 V, measure and record the current.</li>
	<li>Connect each gate line to a battery-powered variable dc voltage source, the source line to the built-in ac voltage source of a lock-in amplifier, and the drain line to the input port of the lock-in amplifier.</li>
	<li>Measure the source to drain conductance for different gate voltage configurations (see Figure 4).
	<ol>
		<li>Globally ramp up the voltages applied to gates BL, BR, PL, SL and DL, by keeping C1 and C2 gates grounded. Record the &#8216;turn-on&#8217; device characteristics.</li>
		<li>Individually ramp down each gate voltage and record the gates &#8216;pinch-off&#8217; characteristics.</li>
		<li>Adjust the gate voltages to electrostatically define a quantum dot by setting the voltages on BL and BR (PL, SL and DL) smaller (greater) than the turn-on voltages. Record the Coulomb blockade characteristics.</li>
	</ol>
	</li>
</ol>

<ol><li>Sze, S. M. Physics of Semiconductor Devices. , Wiley. Interscience, NY. 505-566 (1969).</li>
<li>Moore, G. E. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Cramming+More+Components+onto+Integrated+Circuits%5BTitle%5D)+AND+%22Electronics%22%5BJournal%5D)">Cramming More Components onto Integrated Circuits.</a> Electronics. 38, 114-117 (1965).</li>
<li>Voisin, B., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Few-Electron+Edge-State+Quantum+Dots+in+a+Silicon+Nanowire+Field-Effect+Transistor%5BTitle%5D)+AND+%22Nano+Lett%22%5BJournal%5D)">Few-Electron Edge-State Quantum Dots in a Silicon Nanowire Field-Effect Transistor.</a> Nano Lett. 14 (4), 2094-2098 (2014).</li>
<li>Asenov, A., Brown, A. R., Davies, J. H., Savas, K., Slavcheva, G. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Simulation+of+Instrinsic+Parameter+Fluctuations+in+Decananometer+and+Nanometer-Scale+MOSFETs%5BTitle%5D)+AND+%22IEEE+Trans+Electron+Devices%22%5BJournal%5D)">Simulation of Instrinsic Parameter Fluctuations in Decananometer and Nanometer-Scale MOSFETs.</a> IEEE Trans Electron Devices. 50 (9), 1837-1852 (2003).</li>
<li>Zwanenburg, F. A., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Silicon+Quantum+Electronics%5BTitle%5D)+AND+%22Rev.+Mod.+Phys%22%5BJournal%5D)">Silicon Quantum Electronics.</a> Rev. Mod. Phys. 85 (3), 961-1019 (2013).</li>
<li>Ladd, T. D., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Quantum+computers%5BTitle%5D)+AND+%22Nature%22%5BJournal%5D)">Quantum computers.</a> Nature. 464 (7285), 45-53 (2010).</li>
<li>Piquemal, F. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Genev%C3%A8s%2C+G.+for+a+direct+realization+of+the+quantum+metrological+triangle%5BTitle%5D)+AND+%22Metrologia%22%5BJournal%5D)">Genevès, G. for a direct realization of the quantum metrological triangle.</a> Metrologia. 37 (3), 207-211 (2000).</li>
<li>Angus, S. J., Ferguson, A. J., Dzurak, A. S., Clark, R. G. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Gate-Defined+Quantum+Dots+in+Intrinsic+Silicon%5BTitle%5D)+AND+%22Nano+Lett%22%5BJournal%5D)">Gate-Defined Quantum Dots in Intrinsic Silicon.</a> Nano Lett. 7 (7), 2051-2055 (2007).</li>
<li>Gonzalez-Zalba, M. F., Heiss, D., Podd, G., Ferguson, A. J. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Tunable+aluminium-gated+single+electron+transistor+on+a+doped+silicon-on-insulator+etched+nanowire%5BTitle%5D)+AND+%22Appl.+Phys.+Lett%22%5BJournal%5D)">Tunable aluminium-gated single electron transistor on a doped silicon-on-insulator etched nanowire.</a> Appl. Phys. Lett. 101 (10), 103504-103501 (2014).</li>
<li>Lim, W. H., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Observation+of+the+single-electron+regime+in+a+highly+tunable+silicon+quantum+dot%5BTitle%5D)+AND+%22Appl.+Phys.+Lett%22%5BJournal%5D)">Observation of the single-electron regime in a highly tunable silicon quantum dot.</a> Appl. Phys. Lett. 95 (24), 242102-242103 (2009).</li>
<li>Yang, C. H., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Spin-valley+lifetimes+in+silicon+quantum+dots+with+tunable+valley+splitting%5BTitle%5D)+AND+%22Nat.+Commun%22%5BJournal%5D)">Spin-valley lifetimes in silicon quantum dots with tunable valley splitting.</a> Nat. Commun. 4 (2069), (2013).</li>
<li>Chan, K. W., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Single-electron+shuttle+based+on+a+silicon+quantum+dot%5BTitle%5D)+AND+%22Appl.+Phys.+Lett%22%5BJournal%5D)">Single-electron shuttle based on a silicon quantum dot.</a> Appl. Phys. Lett. 98 (21), 212103-212101 (2011).</li>
<li>Rossi, A., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((An+accurate+single-electron+pump+based+on+a+highly+tunable+silicon+quantum+dot%5BTitle%5D)+AND+%22Nano+Lett%22%5BJournal%5D)">An accurate single-electron pump based on a highly tunable silicon quantum dot.</a> Nano Lett. 14 (6), 3405-3411 (2014).</li>
<li>Pekola, J. P., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Single-electron+current+sources%3A+Toward+a+refined+definition+of+the+ampere%5BTitle%5D)+AND+%22Rev.+Mod.+Phys%22%5BJournal%5D)">Single-electron current sources: Toward a refined definition of the ampere.</a> Rev. Mod. Phys. 85 (4), 1421-1472 (2013).</li>
<li>Giblin, S. P., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Towards+a+quantum+representation+of+the+ampere+using+single+electron+pumps%5BTitle%5D)+AND+%22Nat.+Commun%22%5BJournal%5D)">Towards a quantum representation of the ampere using single electron pumps.</a> Nat. Commun. 3, 930(2012).</li>
<li>Kouwenhoven, L. P., Austing, D. G., Tarucha, S. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Few-electron+quantum+dots%5BTitle%5D)+AND+%22Rep.+Prog.+Phys%22%5BJournal%5D)">Few-electron quantum dots.</a> Rep. Prog. Phys. 64 (6), 701-736 (2001).</li>
<li>Veldhorst, M., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((An+addressable+quantum+dot+qubit+with+fault-tolerant+control+fidelity%5BTitle%5D)+AND+%22Nat.+Nanotech%22%5BJournal%5D)">An addressable quantum dot qubit with fault-tolerant control fidelity.</a> Nat. Nanotech. 9 (12), 981-985 (2014).</li>
<li>Fujiwara, A., Nishiguchi, K., Ono, Y. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Nanoampere+charge+pump+by+single-electron+ratchet+using+silicon+nanowire+metal-oxide-semiconductor+field-effect+transistor%5BTitle%5D)+AND+%22Appl.+Phys.+Lett%22%5BJournal%5D)">Nanoampere charge pump by single-electron ratchet using silicon nanowire metal-oxide-semiconductor field-effect transistor.</a> Appl. Phys. Lett. 92 (4), 042102-1-042102-3 (2008).</li>
<li>Jehl, X., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Hybrid+Metal-Semiconductor+Electron+Pump+for+Quantum+Metrology%5BTitle%5D)+AND+%22Phys.+Rev.+X%22%5BJournal%5D)">Hybrid Metal-Semiconductor Electron Pump for Quantum Metrology.</a> Phys. Rev. X. 3 (2), 021012-1-021012-7 (2013).</li>
<li>Tettamanzi, G. C., Wacquez, R., Rogge, S. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Charge+pumping+through+a+single+donor+atom%5BTitle%5D)+AND+%22New+J.+Phys%22%5BJournal%5D)">Charge pumping through a single donor atom.</a> New J. Phys. 16 (6), 063036-1-063036-17 (2014).</li>
<li>Koppinen, P. J., Stewart, M. D., Zimmerman, N. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Fabrication+and+Electrical+Characterization+of+Fully+CMOS-Compatible+Si+Single-Electron+Devices%5BTitle%5D)+AND+%22IEEE+Trans+Electron+Devices%22%5BJournal%5D)">Fabrication and Electrical Characterization of Fully CMOS-Compatible Si Single-Electron Devices.</a> IEEE Trans Electron Devices. 60 (1), 78-83 (2013).</li>
<li>Fletcher, J. D., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Stabilization+of+single-electron+pumps+by+high+magnetic+fields%5BTitle%5D)+AND+%22Phys.+Rev.+B%22%5BJournal%5D)">Stabilization of single-electron pumps by high magnetic fields.</a> Phys. Rev. B. 86 (15), 155311-1-155311-6 (2012).</li>
<li>Kataoka, M., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Tunable+Nonadiabatic+Excitation+in+a+Single-Electron+Quantum+Dot%5BTitle%5D)+AND+%22Phys.+Rev.+Lett%22%5BJournal%5D)">Tunable Nonadiabatic Excitation in a Single-Electron Quantum Dot.</a> Phys. Rev. Lett. 106 (12), 126801-1-126801-4 (2011).</li>
</ol>

The authors have nothing to disclose.

The protocol reported in this paper describes the techniques to fabricate silicon MOS QDs, as well as the experimental procedures to test their functional integrity and operate them as single-electron pumps. Remarkably, by tailoring the gate design, the same fabrication process can be employed to produce devices suitable for quantum bit readout and control17, as well as charge pumping12,13. We note that many of the process parameters quoted in this article may vary depending on the fabrication tools used (calibration, make or model), as well as on the type of silicon substrate (thickness and background doping density). Quantities such as lithography exposure dose or development time, etching or oxidation duration, have to be carefully calibrated and tested to ensure a reliable yield. Furthermore, it is crucial to avoid cross-contamination arising from the use of the same fabrication tools for different processes. To this end, a number of critical steps are carried out with equipment exclusively dedicated to silicon processing such as metal evaporators, oxygen furnaces and HF baths.
More generally, silicon is drawing a growing interest as the material of choice to realize charge pumps18-20. This is partly due to the attractive perspective of implementing a new quantum-based electric current standard using an industry-compatible silicon process. This would benefit from well-established and reliable integration techniques for scalability, parallelization and driving overhead. Importantly, a full complementary MOS (CMOS) technology, free of traditional metal as the gate material, has shown greatly reduced background charge fluctuations in single-electron devices21. Such fluctuations can be harmful in achieving metrological accuracies.
The protocol discussed here is limited to the realization of MOS nano-devices with metal gates. Therefore, to achieve full industrial compatibility and reduce charge fluctuations, it would be needed to modify the gate deposition techniques and use highly doped polycrystalline silicon as the gate material.
In conclusion, the MOS QD pumps discussed here have recently combined the technological advantage of silicon with very good performance in terms of accurate current generation13. This stems from the high flexibility of the design and fabrication process which allow one to stack multiple gate layers leading to a compact and versatile system. The resulting fine tunability of the electrostatic confinement of the dot together with the potential to reduce background charge fluctuations sets the stage to overcome the main challenges observed in other semiconductor pumps22,23 .

Silicon is the material of choice for most of the modern microelectronics. Its properties, combined with advanced lithographic techniques, have allowed the semiconductor industry to achieve very large-scale integration and deliver billions of transistors per chip. The metal-oxide-semiconductor (MOS) technology1 has been the key of this relentless technological progress2. In brief, it is based on a selectively doped Si substrate which is thermally oxidized to grow a high quality SiO2 gate oxide on which a metal gate electrode is deposited. Recently, it has been shown that the use of a stack of gate oxides could be beneficial3 . While present industry standards have reached minimum feature sizes for gate lengths below 20 nm, it is becoming increasingly evident that, at this level of miniaturization, detrimental quantum mechanical phenomena come into play that may complicate further downscaling4.
Remarkably, silicon is also an excellent host material to exploit the quantum properties of the electron charge and spin5. This has broadened its range of applicability to entirely new fields such as quantum computing6 and quantum electrical metrology7. Among other approaches5, the use of a multi-gate MOS technology8,9 has led to electrostatically-defined quantum dots (QD) whose occupancy can be controlled down to single-electron level10. Unlike the conventional MOS process where just one gate per transistor is needed1, these QDs are defined via a three-layer stack of Al/AlyOx gates which are used to selectively accumulate electrons at the Si/SiO2 interface, as well as provide lateral and vertical confinement11.
Although these devices had been originally developed for quantum computing applications, they have also recently shown promising performances as metrological tools12,13. In the field of quantum electrical metrology, a long-standing goal is the redefinition of the unit ampere in terms of the elementary charge (e) 14. In particular, the emphasis is on the realization of nano-scale charge pumps to clock the transfer of individual electrons timely and accurately. These devices generate macroscopic quantized electric currents, I=nef, where f is the frequency of an external driving oscillator and n is an integer. To date, the best performance has been achieved with a GaAs-based pump by yielding a current in excess of 150 pA with a relative uncertainty of 1.2 parts per million15. Recently, silicon MOS QDs have also stood out for the implementation of highly accurate single-electron pumps thanks to the capability of finely tuning the charge confinement13.
Here, we discuss the protocol used for the fabrication of silicon MOS QDs. Furthermore, the cryogenic set-up used to test the integrity of the devices after fabrication and the one to perform charge pumping experiments are described. Finally, representative measurements of quantized electric current are reported.

<table><tbody><tr><td>Silicon wafers</td><td>TOPSIL</td><td></td><td>4 inch</td></tr><tr><td>Electron-beam lithography machine</td><td>Raith gmbh</td><td></td><td>Raith 150two</td></tr><tr><td>E-beam resist&amp;nbsp;</td><td>MicroChem gmbh</td><td></td><td>PMMA</td></tr><tr><td>Photoresist</td><td>MicroChem gmbh</td><td></td><td>nLOF2020</td></tr><tr><td>Mask aligner</td><td>Quintel</td><td></td><td>Q6000</td></tr><tr><td>Photoresist developer</td><td>MicroChem gmbh</td><td></td><td>AZ826MIF</td></tr></tbody></table>

silicon metal-oxide-semiconductor quantum dots for single-electron pumping

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.

Device Fabrication
The initial microfabrication process (sub-section 1 of the Protocol) is performed on a commercial 4-inch high-purity silicon wafer (n-type doping concentration ≈ 1012 cm-3; resistivity &gt; 10 kΩcm; thickness = 310–340 μm). The aim is to realize the substrate on which the gate electrodes will be deposited. This substrate is made of an intrinsic region capped with field oxide (step 1.1), an n+ region capped with field oxide (step 1.2), an intrinsic region capped with high-quality gate oxide (step 1.3), and a metallized n+ region for ohmic contacts (step 1.4). Figures 1A-D illustrate the main steps of the microfabrication process. Figure 1E shows a microscopic image of a substrate field after microfabrication. The minimum feature size for the lithography at this stage is approximately 4 μm.
The SiO2 oxide layer grown in step 1.1 has a nominal thickness of 100 nm and is used as a passivation layer. The n-type regions that act as ohmic conductors are obtained via phosphorus diffusion. The target doping density is approximately 1019 – 1020 cm-3. The high-quality SiO2 which is selectively grown to be used as gate dielectric has a nominal thickness of 5 nm. The target interface defect density is &lt;1010 eV-1cm-2 at mid-gap. A dedicated and purposely built triple wall furnace is used for this process. This system is designed to minimize contamination from heavy metal ions and mobile alkali ions, as well as prevent moisture from diffusing into the oxidation chamber. In order to form the electrical contacts, aluminum pads are deposited via electron-beam evaporation on part of the n-type regions.
The nanofabrication process (see sub-section 2) is performed on chip substrates obtained by dicing the wafer processed in step 1. The aim is to realize the nano-scale gate electrodes used to electrostatically define the MOS QDs. Each nanofabrication run typically produces 10–15 complete device samples. Scanning electron micrograph (SEM) imaging of 1–2 devices per batch is usually carried out to confirm that the EBL lithography stages have been successful. Since SEM imaging may inject charges in the substrate or in the metallic gates and cause leakages, only a small number of devices is checked in this way, while the rest is electrically tested. Minimum feature size for the lithography at this stage is approximately 35 nm. To achieve good uniformity of the deposited Al films, the metal is evaporated at rates as slow as few angstrom/second, while the substrate is mounted on a rotating stage. This is kept at RT, and the Al grain size is estimated to be of approximately 20 nm. Figure 2A illustrates the main steps of the nanofabrication process. Figure 2B shows a SEM image with which the correct definition of the gate electrodes is verified. In general, one aims at realizing those gates which directly define the QD (BL, BR and PL) with the smallest possible feature size. By contrast, those gates used to define the electron reservoirs (DL and SL) can have larger dimensions to avoid the unintentional discretization of energy levels in the leads. The nano-scale Ti/Pt markers realized in step 2.3 are used as reference for consistent alignment of the three layers of gates. Platinum is chosen for its excellent contrast with respect to the SiO2 surface in the e-beam. Titanium is used to enhance adhesion.
At all stages of the fabrication process, carbon-fiber-tip tweezers are used to handle the chips, in order to reduce the likelihood of destructive electrostatic discharge (ESD).
Finally, in order to perform electrical measurements on individual devices, each chip needs to be cleaved in smaller pieces of about 2 x 2 mm2 (sub-section 3). Each piece is then glued to a custom-made PCB (Rogers R03010 low-loss dielectric) whose pins are connected to the device electrodes through Al wires. Wire bonding is carried out with a wedge bonder machine without heating the chips. The choice of the appropriate bonding parameters is based on two considerations. On the one hand, the wire bond needs to perforate the thermal AlyOx layer and make good metal-to-metal contact with the gate pad. On the other hand, an excessive mechanical stress may result in a punch-trough event which damages the field oxide underneath the gate and cause substrate leakages. During the wiring process, the use of an antistatic bracelet is advisable to prevent ESD. In Figure 3, a chip with 6 individual devices is glued onto the PCB.
Device integrity tests
Before loading a device into a mK temperature measurement platform such as a dilution refrigerator, preliminary electrical tests are performed at 4.2 K to check the integrity of the sample (see sub-section 4 of the Protocol). To this end, the PCB is inserted into an oxygen-free copper enclosure and is mounted onto a dip probe, which is eventually immersed in liquid He.
The initial test is typically a leakage test that is performed sequentially on each gate. A source-measure unit is connected to an individual gate electrode while the others are grounded. The voltage is ramped up to 1.5 V and the current is measured at the source. Within this voltage range, a properly working gate is not supposed to conduct, because the SiO2 layer insulates the metal from the silicon substrate and AlyOx insulates overlapping gates. Typically, oxide breakdown is known to occur for voltages larger than ~4 V, depending on device geometry and oxide thickness. Therefore, if current is detected during the test, it is likely that at least one of the oxide layers is damaged and the device has to be discarded. Usually, less than 10% of the gates show leakages. The yield is known to be affected by the planar extension of the gate electrodes. In particular, the larger the overlap of the gates with the gate oxide region the more likely it will be to have gate-to-substrate leakages. Similarly, the larger the overlap between gates from different layers the more likely the occurrence of gate-to-gate leakages will be. The quoted yield is relevant for gates that occupy an area of about 50 μm2 on the thin oxide and with interlayer overlaps of approximately 0.5 μm2.
Once the device has passed the initial leakage test, the source and drain contacts are connected to a lock-in amplifier and the gates to a modular controllable-voltage battery rack. In this configuration, the device is turned on by globally ramping up all the gate voltages simultaneously. Next, each gate voltage is separately ramped down while keeping the others at high voltages to verify the ability of individual gates to pinch off the current. Figure 4A shows representative traces of these measurements. The absence of either a source-drain conduction pathway or individual gate pinch-off is often an indication of some type of gate damage such as gate explosion or metal discontinuity.
Finally, the source-drain current is measured as a function of source-drain bias and plunger gate voltage to observe the signature of Coulomb blockade16 (see Figure 4B).
Measurements
Once a suitable device has been found, it is removed from the liquid He vessel, and dried with a hot-air gun to avoid formation of moisture which may cause ESD. Finally, it is transferred to a dilution refrigerator.
The experiments are performed in a self-made plastic dilution refrigerator with a base temperature of about 100 mK. The cryostat is in a vacuum chamber immersed in a 4.2 K helium bath. The electrical lines are thermalized at the 1 K pot which is also employed to condense the incoming 3He vapor. In the mixing chamber, the endothermic transfer of 3He atoms from the 3He-rich phase into the 3He-dilute phase allows the system to reach a base temperature of about 100 mK.
As shown in Figure 5, the fridge is equipped with 20 dc lines and 3 rf lines used to connect the room-temperature electronics to the device at low temperature. Five of the dc lines are Thermocoax cables and 15 are twisted pair loom wires. These lines connect the gate electrodes of the sample to battery-powered dc voltage sources. Voltage dividers at RT are used to reduce electrical noise on individual gates. The RF lines are semirigid coaxial cables that are attenuated by 10 dB at 4 K to reduce thermal noise and dc blocked at RT. These lines are connected to the coplanar waveguides of the bias tees on the PCB.
A low-noise transimpedance amplifier and a digital multimeter are used to measure the current generated by the pump. The electronics is connected to the device via battery-powered optoisolators to prevent the formation of ground loops. The RF drive signals are produced by an arbitrary waveform generator whose grounding is isolated from the one of the cryostat via a dc block component (see Figure 5).
The PCB contains 16 pure dc lines and 4 bias tee lines used to combine dc and ac voltages at low temperature. As shown in Figure 3B, RC discrete components are used to realize the tee connection (R = 100 kΩ, C = 10 nF), and 50 Ω-matched integrated coplanar waveguides are used for the propagation of high-frequency signals.
Once the device is at mK temperature, the gate voltages are adjusted so that single-electron occupancy in the QD is attained. In particular, tunnel barriers are formed under gates BL and BR, and an electron accumulation layer is induced under gates PL, SL and DL. To this end, the barrier gate voltages are set below their turn-on values, while the accumulation gates are polarized at a greater-than-turn-on voltage. In this way a QD is formed under gate PL and its planar extension is controlled via gates C1 and C2 whose voltages are kept below their turn-on values to induce electrostatic confinement. Next, the rf signals are turned on to periodically modulate the transparency of the tunnel barrier(s), and the electrochemical potential of the dot. Single-electron pumping is achieved with either one or two sinusoidal driving voltages. In the case of one-signal drive, the driving signal is applied to gate BL to modulate the potential of the tunnel barrier at the left-hand-side of the QD. In the case of the two-signal drive, the ac excitations are applied to gates BL and PL to modulate the potentials of both the left barrier and the QD at the same frequency but with different phases and amplitudes. These additional degrees of freedom allow one to control the direction of the electron transfer13. An iterative process is typically needed to tune the main experimental parameters (i.e., rf drive signal amplitudes/phases and dc gate voltages) and achieve optimal current quantization. Note that neither of the two pumping protocols needs a drain-source bias to perform charge transfers. Hence, the source and drain electrodes are grounded during the pump operation. Figure 6 shows the characteristic current plateaux at integer multiples of ef obtained by applying a two-signal sinusoidal drive to the input barrier (BL) and the plunger (PL) gate. These data are taken at a relatively low driving frequency (10 MHz) for which the tuning of the parameters can be carried out fast. In practice, it is desirable to operate the pump at several hundreds of MHz, typically requiring a much finer parameter optimization13.
<img alt="Microfabrication process diagram; SiO2 and Si layers, photolithography, ohmic contacts, gate oxide." src="/files/ftp_upload/52852/52852fig1.jpg" data-altupdatedat="1787630408000" data-alt="Figure 1"> 
Figure 1. Microfabrication. (A) Schematic illustration of main steps in microfabrication. Cartoons are not drawn to scale. (B) Realization of a doped region for ohmic contacts. (C) Realization of gate oxide. (D) Metallization of ohmic contacts. (E) Microscopic image of an individual field on a chip after the microfabrication process is completed. Field size is 1.2 x 1.2 mm2. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig1large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Static equilibrium in gate layer processing; diagram of spin resist, e-beam lithography, nanostructure." src="/files/ftp_upload/52852/52852fig2.jpg" data-altupdatedat="1787630408000" data-alt="Figure 2"> 
Figure 2. Nanofabrication. (A) Fabrication process for individual gate layers. Cartoons are not drawn to scale. (B) The 3-layer gate nanostructure used for charge pumping experiments. Left: SEM image of a device similar to the one used for the measurements. Right: Schematic cross-sectional views of the device across X-cut and Y-cut. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig2large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Microchip circuit diagram; ΣI=0; integrated circuit; microscopy; data visualization; device setup." src="/files/ftp_upload/52852/52852fig3.jpg" data-altupdatedat="1787630408000" data-alt="Figure 3"> 
Figure 3. Electrical connections to the sample. (A) Layout of the printed circuit board. (B) Magnification of a region of the PCB with a bias-tee (left) and equivalent circuit (right). (C) A chip with 6 individual fields glued on the chip holder and bond wires for electrical connection to the PCB. (D) Microscopic image of an individual field after nanofabrication. (E) SEM image of the gate layout at the center of the gate oxide region. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig3large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Quantum dot transport study; a) Current vs. gate voltage graph; b) Voltage-dependent current map." src="/files/ftp_upload/52852/52852fig4.jpg" data-altupdatedat="1787630408000" data-alt="Figure 4"> 
Figure 4. Preliminary tests. (A) Source-drain ac current (root mean square) as a function of different gate voltages. Traces are measured with a lock-in amplifier with 50 μVRMS excitation at 113.17 Hz. For individual gate voltage traces the remaining gate voltages are fixed at 2.0 V, except for VC1 = VC2 = 0.0 V. (B) Color map of source-drain current as a function of plunger gate voltage and source-drain bias voltage. VSL = 1.5 V, VDL = 1.15 V, VBL = 0.78 V, VBR = 0.85 V, VC1 = VC2 = 0.0 V. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig4large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Cryogenic experimental setup diagram; RF, transimpedance amplifier, He bath, Vgate measurement." src="/files/ftp_upload/52852/52852fig5.jpg" data-altupdatedat="1787630408000" data-alt="Figure 5"> 
Figure 5. Schematic of the measurement set-up. Twenty dc lines (green) and three coaxial rf lines (black) connect the RT electronics to the PCB. The drain of the pump (purple) is connected to a transimpedance amplifier and to a digital multimeter via an optoisolator, while the source contact (red) is grounded. Separate ground connections (indicated with different symbols) are used for the electronic instrumentation and the cryostat electric lines. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig5large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Current-voltage graph, electron transport quantization, stair-step pattern, I-V measurement analysis." src="/files/ftp_upload/52852/52852fig6.jpg" data-altupdatedat="1787630408000" data-alt="Figure 6"> 
Figure 6. Current quantization. Pumped current as a function of VPL for two-signal sinusoidal drive at f = 10 MHz applied to gates BL and PL. Phase difference = 49 deg, VRFPL = VRFBL = 0.31 Vpp. The ideal position of the pumping plateaux at integer multiples of ef are shown as red horizontal lines. <a href="https://www.jove.com/files/ftp_upload/52852/52852fig6large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>

The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by ...

The overall goal of the following experiment is to fabricate silicon-based metal oxide semiconductor quantum dots and to operate them as single electron pumps. This is achieved by fabricating silicon nano transistors with a multi-layer gait technique, which allows one to electrostatically control individual electrons confined within quantum dots and manipulate their transfer rate. As a second step.The fabricated devices are tested at liquid helium temperature to check their structural integrity. The observation of cool on blockade in the current voltage characteristics indicate satisfactory device functionalities. The results show that a quantum dot can be operated as a single electron pump in a Malik Kelvin measurement platform.When the transparency of the entrance barrier is driven with an AC signal. This is evidenced by the appearance of signature current plateaus. Silicon Nanoelectronics is at the heart of the information age that we all live in.Remarkably silicon is also an excellent host material for quantum based applications such as quantum computing and quantum electrical metrology. Here at UNSW, we've developed the technology to turn conventional transistors into quantum devices. We can confine electrons in a tiny region in silicone with the size of only a few tens of nanometers.This is something people call a quantum dot. We use such quantum dots to precisely catch an electron from the source lead and push it to the drain lead, and repeating this process extremely fast will be used in future to generate the most accurate electric current in the world. A longstanding goal in electrical metrology is the redefinition of the unit of electric current DM pair by linking its value to a true constant of nature, such as the electron charge.The presented techniques explain how to manufacture and operate silicone quantum devices to implement this link. Nanoscale devices used in this work are fabricated using a protocol largely compatible with industrial CMOs processes. However, unlike standard CMOs devices, we add a metallic gate stack, which allows one to spatially confine individual electrons.Our protocol demonstrates how to test and operate a quantum dot based single electron pump. The key ingredient for its success is to find control over the electrostatic potential of the dot, as well as over the transparency of the tunnel barriers. Multiple RF signals are typically used to drive the transfer of single electrons from and into tdot.The great advantage of our multi-layer gated devices over alternative implementations like metal devices or three five semiconductors, is that we achieved exquisite control over the electrostatic confinement of the dot. This has been the key to suppress errors in the pumping mechanism. To create a field oxide layer on a silicon wafer, have an oxidation furnace ready at 900 degrees Celsius.Start with a properly cleaned two inch silicon wafer. Place the wafer in the furnace and begin the oxidation steps. The oxidation steps take approximately one and one quarter hours.When done, prepare to deposit a layer of HDMS on the wafer to begin creating the omic contacts. To do this, place the wafer on a hot plate at 110 degrees Celsius for one minute. Also, pour about 50 milliliters of HDMS into a glass beak.When both are ready, place the wafer and the beaker in a vacuum chamber to deposit a few nanometer thick layer of HDMS on the wafer. After removing the wafer from the vacuum chamber, move it to a spin coder.There. Spin a two to four micrometer layer of photoresist on both the back and front of the wafer.Continue by moving the wafer from the spin coer to a mask aligner. Position the wafer and set up the mask to pattern the contacts for this process. Use ultraviolet light to transfer this omic contact pattern to the wafer.After patterning, move the wafer to a hot plate. Bake the wafer at 110 degrees Celsius for one minutes after the post bake. Develop the wafer for one to two minutes and rinse it in deionized water before taking it to a plasma etcher.Perform an oxygen plasma etch for 20 minutes at 340. Millitorr with 50 watt incident power and less than one watt reflected power. After the plasma etch, have ready a 15 to one buffered hydrofluoric acid solution At 30 degrees Celsius.Etch the oxide for four to five minutes, assuming an edge rate of 20 nanometers per minute at 30 degrees Celsius. When done, rinse the wafer in deionized water For five minutes, blow dry the wafer with dry nitrogen before continuing. Next, have ready vessels of acetone and isopropanol.Remove the photoresist by immersing the wafer in acetone for five minutes. Follow this by rinsing it in isopropanol for another five minutes. Move the dry wafer to a furnace at 1000 degrees Celsius that is equipped with a phosphorus source.Place the wafer inside with nitrogen gas flow for 30 to 45 minutes depending on the desired doping density. After recovering the wafer, prepare to remove the contaminated oxide layer. Have ready a vessel of hydrofluoric acid diluted in water and a vessel of deionized water each sufficient to immerse the wafer.Immerse the wafer in the acid for three to four minutes, and then rinse it in the water for 10 minutes. Return the wafer to the oxidation furnace held at 900 degrees there. Go through the oxidation steps over the course of about one and one quarter hours after oxidation.The next step is to form the gait oxide deposit a few nanometer thick layer of HDMS on the wafer. Next, move to a spin coder spin coat, two to four micrometers of photoresist on both sides of the wafer. Once again, take the wafer to the mask aligner there.Expose the wafer to ultraviolet light to transfer the required pattern. After developing the wafer, place it in an oxygen plasma etch for 20 minutes at 340 millitorr. Follow this with etching in a 15 to one buffered hydrofluoric acid solution at 30 degrees Celsius.Place the wafer in the solution for three to four minutes, then rinse the wafer in deionized water for five minutes. After drying the wafer, immerse it in acetone for five minutes. To remove the photoresist, rinse the wafer in isopropanol for five minutes.After drying the wafer in nitrogen gas, take it to a dedicated 800 degree Celsius furnace and place it inside the oxidation steps. Take an hour to an hour and 15 minutes depending on the desired oxide thickness. Before gait patterning, the wafer should undergo metalization of source and drain contacts and dicing into individual chips.These 10 millimeter by two millimeter chips have also been patterned with alignment markers for electron beam lithography patterning the aluminum gates takes three passes and begins with spin coating. For each pass, spin polymethyl methacrylate a four resist to a thickness of 150 to 200 nanometers. After coating, transfer the chip to a hot plate at 180 degrees Celsius.Bake the chip for 90 seconds before continuing. Now move the chip to an electron beam lithograph. During lithography, use different parameters for high and low resolution.This is the pattern for the gait layout. In this experiment, develop the resist with the solution of isobutyl, ketone and isopropanol. In a ratio of one to three, immerse the chip in the solution for 40 to 60 seconds.Rinse the chip in isopropanol for 20 seconds and blow dry with nitrogen. Next, take the chip to a thermal evaporator. Prepare to evaporate aluminum for the first pass.Evaporate the aluminum at 0.1 to 0.4 nanometers per second to a target thickness of 25 to 35 nanometers. After the evaporation proceed to lift off the metal, have a vessel of ethyl two parone ready on a hot plate at 80 degrees Celsius and soak the chip for one hour. Next, rinse the chip in isopropanol for two minutes.Perform aluminum oxidation on a hot plate at 150 degrees Celsius. Place the dry chip on the hot plate for five to 10 minutes. Complete the first pass by cleaning the chip, spin clean, using acetone and isopropanol at 7, 500 RPM for 30 seconds.This schematic provides an overview of what was done in the first pass. During a second pass, evaporate a 45 to 65 nanometer layer of aluminum. In the third pass, evaporate a 75 to 90 nanometer layer of aluminum to realize the three layer gate stack.In order to perform the integrity tests, a chip must be properly mounted on a printed circuit board, mount a chip, and make electrical connections between it and the printed circuit. Next, mount the printed circuit board on a dip probe. Wire the probe to allow electrical connection to the device gates.When the probe is ready, obtain a vessel containing liquid helium and slowly immerse the probe to avoid excessive helium boil off. This schematic illustrates the connections for the leakage test. Using the room temperature electrodes ground all gates except for one connected to a source measure unit.Sweep the source measure unit voltage from zero to 1.5 volts in steps of 0.1 volts to measure and record the current. If no current is detected, the device passes the leakage test. For the next test, connect each gate to a variable DC voltage source.Connect the source line to the input port of a lock-in amplifier. Also connect the drain line to the built-in AC voltage source of the lock-in amplifier. Measure the turn on characteristics by simultaneously ramping up the gate voltages applied to BL br pl sl and DL while keeping C one and C two grounded.Record the device turn on characteristics. This is a sample trace for this measurement. Next, ramp down each gate voltage individually to record its pinch off characteristics where this measurement BL is ramped down.Here our representative results for the turnon and pinch off characteristics in the plot. The RMS source drain AC current is given as a function of the gate voltage. The gates are labeled in the schematic.The source and drain contacts are connected to a lock-in amplifier with 50 microvolts RMS excitation at about 113 hertz and the gates are connected to a modular controllable voltage battery rack. Gate C one and C two are held at zero volts while the others are held at two volts. This is a representative measurement of source drain current represented on a color spectrum as a function of source drain bias and plunger gate voltage.When a quantum. is formed under the plunger gate, it clearly reveals the characteristic signature of ulam blockade. Single electron pumping can be achieved when a device is operated in a millikelvin temperature measurement platform equipped with high frequency electrical lines.In this experiment, the device is driven with the two signal 10 megahertz sinusoidal drive at the input barrier and the plunger gate. The characteristic current plateaus at integer multiples of the electron charge and the frequency are the signature of quantized charge transfers. Most of the process parameters courses in this protocol may vary depending on the fabrication tools used as well as on the type of the silicon substrate.Quantities such as lithography exposure dose, or development time etching or oxidation duration have to be carefully calibrated and tested to ensure a reliable yield. During the fabrication process flow, it's crucial to avoid cross-contamination between fabrication equipment for different processes. To avoid this, we have a number of tools exclusively dedicated to silicon processing, such as metal evaporators, oxidation furnaces, and HF baths.The results shown for the current quantization are taken at a relatively long driving frequency of 10 megahertz for which the tuning of the experimental parameters can be carried out fast. In practice, it is desirable to operate the pump at several hundreds of megahertz. It is important to mention that this typically requires a much finer and more time consuming parameter optimization.Following the fabrication process and the measurement techniques discussed in this video, we have been able to generate a microscopic electric current with record accuracy levels among silicon-based systems. This sets enormous promises for the future redefinition of the unit of current, solely based on quantum mechanical principles.Pulse. We are currently looking into replacing the normal metal gates in our devices by poly crystalline silicone.This likely suppresses the background charge noise we currently observe. Our aim is that the resulting improved stability and accuracy of the electron pump. We will then meet the extreme meteorological requirements of a new world current standard.The techniques we've presented in this video show the great potential of silicon-based nano technology for quantum devices. Silicon is drawing more and more interest as the material of choice for charge pumping, and this is due to the attraction of implementing a new current standard using industry compatible silicon processes, which would benefit from the very well established integration techniques early available for system scalability.

silicon-metal-oxide-semiconductor-quantum-dots-for-single-electron

Research

JoVE Journal

Engineering

We describe the preparation of colloidal quantum dots with minimized hydrodynamic size for single-molecule fluorescence imaging.  Compared to conventional quantum dots, these nanoparticles are similar in size to globular proteins and are optimized for single-molecule brightness, stability against photodegradation, and resistance to nonspecific binding to proteins and cells.

Compact Quantum Dots for Single-molecule Imaging

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

Resonant excitation of a single self-assembled quantum dot can be achieved using an excitation mode orthogonal to the fluorescence collection mode. We demonstrate a method using the waveguide and Fabry-Perot modes of a planar microcavity surrounding the quantum dots. The method allows complete freedom in the detection polarization.

Resonance Fluorescence of an InGaAs Quantum Dot in a Planar Cavity Using Orthogonal Excitation and Detection

We demonstrate an all-electronic method to observe nanosecond-resolved charge dynamics of dopant atoms in silicon with a scanning tunneling microscope.

All-electronic Nanosecond-resolved Scanning Tunneling Microscopy: Facilitating the Investigation of Single Dopant Charge Dynamics

Here, we present a protocol to control the carrier number in solids by using the electrolyte.

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

A protocol is presented for fabricating high-performance, pure blue ZnCdS/ZnS-based quantum dots light-emitting diodes by employing an autoxidized aluminum cathode.

Enhanced Electron Injection and Exciton Confinement for Pure Blue Quantum-Dot Light-Emitting Diodes by Introducing Partially Oxidized Aluminum Cathode

Quantum integrated circuits (QICs) consisting of array of planar and ballistic Josephson junctions (JJs) based on In0.75Ga0.25As two-dimensional electron gas (2DEG) is demonstrated. Two different methods for fabrication of the two-dimensional (2D) JJs and QICs are discussed followed by the demonstration of quantum transport measurements in sub-Kelvin temperatures.

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

The gradient echo memory is a protocol for storing optical quantum states of light in atomic ensembles. Quantum memory is a key element of a quantum repeater, which can extend the range of quantum key distribution. We outline the operation of the scheme when implemented in a 3-level atomic ensemble.

Gradient Echo Quantum Memory in Warm Atomic Vapor

Scanning-probe single-electron capacitance spectroscopy facilitates the study of single-electron motion in localized subsurface regions. A sensitive charge-detection circuit is incorporated into a cryogenic scanning probe microscope to investigate small systems of dopant atoms beneath the surface of semiconductor samples.

Scanning-probe Single-electron Capacitance Spectroscopy

A technique was developed that removes Ni/Au contact metal films from their substrate to allow for the examination and characterization of the contact/substrate and contact/NW interfaces of single GaN nanowire devices.

Analysis of Contact Interfaces for Single GaN Nanowire Devices

Learn to fabricate silicon metal-oxide-semiconductor quantum dots and operate them as single-electron pumps using multi-layer gate techniques. This method enables precise control of electron transfer for quantum electrical metrology applications.

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

Explore More Videos