Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

The overall goal of the following experiment is to fabricate silicon-based metal oxide semiconductor quantum dots and to operate them as single electron pumps. This is achieved by fabricating silicon nano transistors with a multi-layer gait technique, which allows one to electrostatically control individual electrons confined within quantum dots and manipulate their transfer rate. As a second step.

The fabricated devices are tested at liquid helium temperature to check their structural integrity. The observation of cool on blockade in the current voltage characteristics indicate satisfactory device functionalities. The results show that a quantum dot can be operated as a single electron pump in a Malik Kelvin measurement platform.

When the transparency of the entrance barrier is driven with an AC signal. This is evidenced by the appearance of signature current plateaus. Silicon Nanoelectronics is at the heart of the information age that we all live in.

Remarkably silicon is also an excellent host material for quantum based applications such as quantum computing and quantum electrical metrology. Here at UNSW, we've developed the technology to turn conventional transistors into quantum devices. We can confine electrons in a tiny region in silicone with the size of only a few tens of nanometers.

This is something people call a quantum dot. We use such quantum dots to precisely catch an electron from the source lead and push it to the drain lead, and repeating this process extremely fast will be used in future to generate the most accurate electric current in the world. A longstanding goal in electrical metrology is the redefinition of the unit of electric current DM pair by linking its value to a true constant of nature, such as the electron charge.

The presented techniques explain how to manufacture and operate silicone quantum devices to implement this link. Nanoscale devices used in this work are fabricated using a protocol largely compatible with industrial CMOs processes. However, unlike standard CMOs devices, we add a metallic gate stack, which allows one to spatially confine individual electrons.

Our protocol demonstrates how to test and operate a quantum dot based single electron pump. The key ingredient for its success is to find control over the electrostatic potential of the dot, as well as over the transparency of the tunnel barriers. Multiple RF signals are typically used to drive the transfer of single electrons from and into tdot.

The great advantage of our multi-layer gated devices over alternative implementations like metal devices or three five semiconductors, is that we achieved exquisite control over the electrostatic confinement of the dot. This has been the key to suppress errors in the pumping mechanism. To create a field oxide layer on a silicon wafer, have an oxidation furnace ready at 900 degrees Celsius.

Start with a properly cleaned two inch silicon wafer. Place the wafer in the furnace and begin the oxidation steps. The oxidation steps take approximately one and one quarter hours.

When done, prepare to deposit a layer of HDMS on the wafer to begin creating the omic contacts. To do this, place the wafer on a hot plate at 110 degrees Celsius for one minute. Also, pour about 50 milliliters of HDMS into a glass beak.

When both are ready, place the wafer and the beaker in a vacuum chamber to deposit a few nanometer thick layer of HDMS on the wafer. After removing the wafer from the vacuum chamber, move it to a spin coder.There. Spin a two to four micrometer layer of photoresist on both the back and front of the wafer.

Continue by moving the wafer from the spin coer to a mask aligner. Position the wafer and set up the mask to pattern the contacts for this process. Use ultraviolet light to transfer this omic contact pattern to the wafer.

After patterning, move the wafer to a hot plate. Bake the wafer at 110 degrees Celsius for one minutes after the post bake. Develop the wafer for one to two minutes and rinse it in deionized water before taking it to a plasma etcher.

Perform an oxygen plasma etch for 20 minutes at 340. Millitorr with 50 watt incident power and less than one watt reflected power. After the plasma etch, have ready a 15 to one buffered hydrofluoric acid solution At 30 degrees Celsius.

Etch the oxide for four to five minutes, assuming an edge rate of 20 nanometers per minute at 30 degrees Celsius. When done, rinse the wafer in deionized water For five minutes, blow dry the wafer with dry nitrogen before continuing. Next, have ready vessels of acetone and isopropanol.

Remove the photoresist by immersing the wafer in acetone for five minutes. Follow this by rinsing it in isopropanol for another five minutes. Move the dry wafer to a furnace at 1000 degrees Celsius that is equipped with a phosphorus source.

Place the wafer inside with nitrogen gas flow for 30 to 45 minutes depending on the desired doping density. After recovering the wafer, prepare to remove the contaminated oxide layer. Have ready a vessel of hydrofluoric acid diluted in water and a vessel of deionized water each sufficient to immerse the wafer.

Immerse the wafer in the acid for three to four minutes, and then rinse it in the water for 10 minutes. Return the wafer to the oxidation furnace held at 900 degrees there. Go through the oxidation steps over the course of about one and one quarter hours after oxidation.

The next step is to form the gait oxide deposit a few nanometer thick layer of HDMS on the wafer. Next, move to a spin coder spin coat, two to four micrometers of photoresist on both sides of the wafer. Once again, take the wafer to the mask aligner there.

Expose the wafer to ultraviolet light to transfer the required pattern. After developing the wafer, place it in an oxygen plasma etch for 20 minutes at 340 millitorr. Follow this with etching in a 15 to one buffered hydrofluoric acid solution at 30 degrees Celsius.

Place the wafer in the solution for three to four minutes, then rinse the wafer in deionized water for five minutes. After drying the wafer, immerse it in acetone for five minutes. To remove the photoresist, rinse the wafer in isopropanol for five minutes.

After drying the wafer in nitrogen gas, take it to a dedicated 800 degree Celsius furnace and place it inside the oxidation steps. Take an hour to an hour and 15 minutes depending on the desired oxide thickness. Before gait patterning, the wafer should undergo metalization of source and drain contacts and dicing into individual chips.

These 10 millimeter by two millimeter chips have also been patterned with alignment markers for electron beam lithography patterning the aluminum gates takes three passes and begins with spin coating. For each pass, spin polymethyl methacrylate a four resist to a thickness of 150 to 200 nanometers. After coating, transfer the chip to a hot plate at 180 degrees Celsius.

Bake the chip for 90 seconds before continuing. Now move the chip to an electron beam lithograph. During lithography, use different parameters for high and low resolution.

This is the pattern for the gait layout. In this experiment, develop the resist with the solution of isobutyl, ketone and isopropanol. In a ratio of one to three, immerse the chip in the solution for 40 to 60 seconds.

Rinse the chip in isopropanol for 20 seconds and blow dry with nitrogen. Next, take the chip to a thermal evaporator. Prepare to evaporate aluminum for the first pass.

Evaporate the aluminum at 0.1 to 0.4 nanometers per second to a target thickness of 25 to 35 nanometers. After the evaporation proceed to lift off the metal, have a vessel of ethyl two parone ready on a hot plate at 80 degrees Celsius and soak the chip for one hour. Next, rinse the chip in isopropanol for two minutes.

Perform aluminum oxidation on a hot plate at 150 degrees Celsius. Place the dry chip on the hot plate for five to 10 minutes. Complete the first pass by cleaning the chip, spin clean, using acetone and isopropanol at 7, 500 RPM for 30 seconds.

This schematic provides an overview of what was done in the first pass. During a second pass, evaporate a 45 to 65 nanometer layer of aluminum. In the third pass, evaporate a 75 to 90 nanometer layer of aluminum to realize the three layer gate stack.

In order to perform the integrity tests, a chip must be properly mounted on a printed circuit board, mount a chip, and make electrical connections between it and the printed circuit. Next, mount the printed circuit board on a dip probe. Wire the probe to allow electrical connection to the device gates.

When the probe is ready, obtain a vessel containing liquid helium and slowly immerse the probe to avoid excessive helium boil off. This schematic illustrates the connections for the leakage test. Using the room temperature electrodes ground all gates except for one connected to a source measure unit.

Sweep the source measure unit voltage from zero to 1.5 volts in steps of 0.1 volts to measure and record the current. If no current is detected, the device passes the leakage test. For the next test, connect each gate to a variable DC voltage source.

Connect the source line to the input port of a lock-in amplifier. Also connect the drain line to the built-in AC voltage source of the lock-in amplifier. Measure the turn on characteristics by simultaneously ramping up the gate voltages applied to BL br pl sl and DL while keeping C one and C two grounded.

Record the device turn on characteristics. This is a sample trace for this measurement. Next, ramp down each gate voltage individually to record its pinch off characteristics where this measurement BL is ramped down.

Here our representative results for the turnon and pinch off characteristics in the plot. The RMS source drain AC current is given as a function of the gate voltage. The gates are labeled in the schematic.

The source and drain contacts are connected to a lock-in amplifier with 50 microvolts RMS excitation at about 113 hertz and the gates are connected to a modular controllable voltage battery rack. Gate C one and C two are held at zero volts while the others are held at two volts. This is a representative measurement of source drain current represented on a color spectrum as a function of source drain bias and plunger gate voltage.

When a quantum. is formed under the plunger gate, it clearly reveals the characteristic signature of ulam blockade. Single electron pumping can be achieved when a device is operated in a millikelvin temperature measurement platform equipped with high frequency electrical lines.

In this experiment, the device is driven with the two signal 10 megahertz sinusoidal drive at the input barrier and the plunger gate. The characteristic current plateaus at integer multiples of the electron charge and the frequency are the signature of quantized charge transfers. Most of the process parameters courses in this protocol may vary depending on the fabrication tools used as well as on the type of the silicon substrate.

Quantities such as lithography exposure dose, or development time etching or oxidation duration have to be carefully calibrated and tested to ensure a reliable yield. During the fabrication process flow, it's crucial to avoid cross-contamination between fabrication equipment for different processes. To avoid this, we have a number of tools exclusively dedicated to silicon processing, such as metal evaporators, oxidation furnaces, and HF baths.

The results shown for the current quantization are taken at a relatively long driving frequency of 10 megahertz for which the tuning of the experimental parameters can be carried out fast. In practice, it is desirable to operate the pump at several hundreds of megahertz. It is important to mention that this typically requires a much finer and more time consuming parameter optimization.

Following the fabrication process and the measurement techniques discussed in this video, we have been able to generate a microscopic electric current with record accuracy levels among silicon-based systems. This sets enormous promises for the future redefinition of the unit of current, solely based on quantum mechanical principles.Pulse. We are currently looking into replacing the normal metal gates in our devices by poly crystalline silicone.

This likely suppresses the background charge noise we currently observe. Our aim is that the resulting improved stability and accuracy of the electron pump. We will then meet the extreme meteorological requirements of a new world current standard.

The techniques we've presented in this video show the great potential of silicon-based nano technology for quantum devices. Silicon is drawing more and more interest as the material of choice for charge pumping, and this is due to the attraction of implementing a new current standard using industry compatible silicon processes, which would benefit from the very well established integration techniques early available for system scalability.