High-level Synthesis
High-level Synthesis - Related Videos
09:43
Measurement of Heme Synthesis Levels in Mammalian Cells
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Cited by 12 •
2015
Altered intracellular heme levels are associated with common diseases such as cancer. Thus, there is a need to measure heme biosynthesis levels in diverse cells. The goal of this protocol is to provide a fast and sensitive method to measure and compare the levels of heme synthesis in different cells.
14:53
Analysis of Global RNA Synthesis at the Single Cell Level following Hypoxia
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Cited by 2 •
2014
We describe a technique for analysis of global RNA synthesis in hypoxia using imaging. Click-chemistry labeling of RNA has not previously been performed under hypoxia and allows visualization of global RNA changes at the single cell level. This approach complements the existing averaged RNA techniques, allowing direct visualization of cell-to-cell changes in global RNA synthesis.
06:55
Synthesis of Cyclic Polymers and Characterization of Their Diffusive Motion in the Melt State at the Single Molecule Level
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2016
A protocol for the synthesis and characterization of diffusive motion of cyclic polymers at the single molecule level is presented.
07:26
Synthesis and Microdiffraction at Extreme Pressures and Temperatures
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Cited by 5 •
2013
The laser heated diamond anvil cell combined with synchrotron micro-diffraction techniques allows researchers to explore the nature and properties of new phases of matter at extreme pressure and temperature (PT) conditions. Heterogeneous samples can be characterized in situ under high pressure by 2D mapping and combined powder, single-crystal and multigrain diffraction approaches.
12:55
Millifluidics for Chemical Synthesis and Time-resolved Mechanistic Studies
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Cited by 8 •
2013
Millifluidic devices are utilized for controlled synthesis of nanomaterials, time-resolved analysis of reaction mechanisms and continuous flow catalysis.
FAQs
High-level synthesis examines operations and data dependencies to determine which computations must precede others, then schedules them under execution constraints. It also assigns computations to hardware resources, shaping the design’s execution pattern. Those decisions influence latency and throughput while also affecting the area and power required by the resulting hardware, making scheduling and resource assignment central to hardware optimization.
Execution constraints define the conditions under which operations can be scheduled and resources assigned. Because HLS balances latency, throughput, area, and power, changing a constraint can shift the design toward a different trade-off rather than improving every metric simultaneously. Engineers therefore use these constraints to guide the generated hardware toward the requirements of a particular computational application.
The main difference is the level at which engineers express the design. HLS begins with an algorithmic description and produces RTL after analyzing and organizing its computations, whereas direct RTL work starts closer to hardware implementation. This higher abstraction can shorten development cycles while still providing an RTL design that can be implemented on digital devices.
An HLS workflow starts with an algorithmic description in a high-level language. The system analyzes operations, dependencies, and execution constraints, then schedules computations and maps them to hardware resources. It generates RTL code for implementation on an FPGA or application-specific integrated circuit, after which engineers can apply systematic optimization and verification.
Common targets include signal-processing pipelines, machine-learning accelerators, control systems, and other computationally intensive applications. HLS is particularly relevant when engineers need to move an algorithmic design onto an FPGA or application-specific integrated circuit while considering latency, throughput, area, or power. These application areas illustrate how one design approach spans data processing and system control.
Engineers can evaluate the generated design through the same factors used to guide optimization: latency, throughput, area, and power. They should also consider whether the hardware correctly reflects the intended algorithm, since HLS supports systematic verification as well as optimization. This evaluation connects the generated RTL to practical implementation decisions for digital devices.