Name: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology (Video) | JoVE Journal
Uploaded: 2015-12-07T13:00:00.000+00:00
Duration: 9 min 20 s
Description: Learn to fabricate low-temperature carbon nanotube vertical interconnects using standard semiconductor techniques. This method enables integration of vertically aligned CNTs into integrated circuits for advanced electronics applications.

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5 minutes

Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

Caution: Please consult all relevant material safety data sheets (MSDS) before use. Several of the chemicals used in this fabrication process are acutely toxic and carcinogenic. Nanomaterials may have additional hazards compared to their bulk counterpart. Please use all appropriate safety practices when working with equipment, chemicals or nanomaterials, including the use of engineering controls (fume hood) and personal protective equipment (safety glasses, gloves, cleanroom clothes).
1. Alignment Marker Definition for Lithography
<ol>
	<li>Start with single-sided polished industrial grade Si(100) wafers with either n or p-type doping.</li>
	<li>Coat the wafer with 1.4 &#181;m of positive photoresist. Perform a 90 sec hexamethyldisilazane (HMDS) treatment at 130 &#176;C to promote adhesion of the photoresist, followed by cooling of the wafer on a cold plate, spin-coating at the appropriate speed (3,500 rpm), and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool expose the alignment markers, exposure dose 120 mJ/cm2.</li>
	<li>Perform a single puddle development process. Perform a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C to cure the resist.</li>
	<li>Use a microscope to inspect if the openings in the resist are of the correct dimensions.</li>
	<li>Etch 120 nm of Si using chlorine plasma etching. This thickness gives good contrast for the automatic alignment systems of the exposure tool used in this work. For example using an inductive coupled plasma (ICP): 20/40 sccm O2/CF4, 5 mTorr, 60/500 W platen/ICP RF power, 10 sec oxide breakthrough etching, followed by 80/40 sccm Cl2/HBr, 60 mTorr, 20/500 W platen/ICP RF power, 35 sec Si etch.</li>
	<li>Use an oxygen plasma stripper to remove the photoresist (1 kW, 400 sccm O2 with endpoint detection and 2 min overetch). As the photoresist is cured by the plasma normal solvent like acetone cannot be used.</li>
	<li>Clean the wafers. First put them for 10 min in 99% HNO3, followed by rinsing in DI water till the resistivity of the water is 5 M&#937; (organic clean). After this clean the wafers for 10 min in 65% HNO3 at 110 &#176;C, followed by rinsing with DI water till the resistivity of the water is 5 M&#937; (metal clean). Use a rinser dryer to dry the wafers.</li>
</ol>
2. Bottom Metal and Interlayer Dielectric Deposition
<ol>
	<li>Use magnetron sputtering to deposit the bottom metal layer of the test via. A stack of three metal layers needs to be deposited: 500 nm of Ti, 50 nm of TiN, and 100 nm Ti. The first Ti layer is to reduce the resistance of the stack, the TiN is the actual support layer for CNT growth, and the top Ti is to protect the TiN against plasma damage when etching the SiO2 layer12. Perform Ti sputtering using a pure Ti target with Ar-plasma at a substrate temperature of 350 &#176;C. For TiN reactive sputtering use a combination of Ar and N2, again at 350 &#176;C substrate temperature.</li>
	<li>Using plasma-enhanced chemical vapor deposition (PECVD), deposit a 1 &#181;m thick layer of SiO2. Here tetraethyl orthosilicate (TEOS) is used as precursor at a platen temperature of 350 &#176;C.
	<ol>
		<li>Check the thickness of the SiO2 layer using an appropriate tool, for instance a reflectometer or ellipsometer.</li>
	</ol>
	</li>
	<li>Coat the wafer with 1.4 &#181;m of positive photoresist, starting with a 90 sec HMDS treatment at 130 &#176;C, followed by cooling of the wafer on a cold plate, spin-coating at the appropriate speed (3,500 rpm), and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool, expose the desired pattern of openings, which will be later etched into the SiO2 to form the vias, aligned to the alignment markers, exposure dose 140 mJ/cm2.</li>
	<li>Perform a single puddle development process starting with a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C.</li>
	<li>Use a microscope to inspect if the openings in the resist are of the correct dimensions and if the overlay to the alignment markers is correct.</li>
	<li>Plasma etch the contact openings in the SiO2. For example, use a triode plasma etcher with C2F6/CHF3 36/144 sccm at 180 mTorr and 300 W RF power. If necessary, perform etch rate tests on a test wafer in order to minimize over etching to 5%-10% in time. 
	Note: Although the Ti is resistant to reactive etching in this fluorine chemistry, prolonged exposure to the plasma will result in physical etching of the Ti layer. If the TiN layer is exposed to the plasma this will have a negative influence on the growth of the CNT12. Do not use wet etching as this will result in too much widening of the openings, making the top metallization in part 4 problematic.</li>
	<li>Remove the sacrificial Ti layer by wet etching in 0.55% HF for 60 sec. After etching rinse the wafers with DI water till the water resistivity is 5 M&#937; and use a rinser dryer to dry the wafers. 
	Note: Using a microscope it can be checked if the Ti layer is etched, the TiN layer will have a gold-brown color while the Ti is metallic grey.</li>
</ol>
3. Catalyst Deposition and CNT Growth
<ol>
	<li>Evaporate 5 nm of Co using an e-beam evaporator. Pump down till at least 2x10-6 Torr, and heat the wafers to 60 &#176;C using lamps under vacuum before depositing to remove any water film. The photo-resist used to define the contact openings is kept on the wafer to provide self-alignment of the catalyst to the contact openings in the SiO2.</li>
	<li>Remove the Co outside the contact openings by lift-off. For Co it was found that tetrahydrofuran (THF) gives the best lift-off results and growth at low temperatures. N-methyl-2-pyrrolidone (NMP), which was previously used for lift-off after Fe evaporation, was found to damage the Co too such an extent to prevent any aligned CNT growth. Put the wafer for 15 min in an ultrasonic bath with THF at 35 &#176;C. Rinse with DI water for 5 min and dry using a spinner or nitrogen gun.</li>
	<li>Inspect the wafer underneath a microscope and check for resist residues. If residues remain perform a longer ultrasonic treatment in THF, and optionally use a special soft cotton swab for lift-off purposes to manually wipe away residues.</li>
	<li>Perform CNT growth using low-pressure chemical vapor deposition (LPCVD). Use the following recipe: 8 min pre-anneal at 350 &#176;C with 700 sccm H2 at 80 mbar, followed by CNT growth by adding 50 sccm C2H2. At 350 &#176;C, 60 min of growth gives roughly 1 &#181;m of CNT. If necessary perform a test growth to tune the height, which should be the same thickness as the SiO2 layer. Cool down the reactor and purge using N2.</li>
	<li>Use a scanning electron microscope to check the height of the CNT inside the openings under 45&#176; tilt, or by preparing a cross-section.</li>
	<li>Inspect the samples using Raman spectroscopy to determine the crystallinity of the CNT18.</li>
</ol>
4. Topside Metallization
<ol>
	<li>Use magnetron sputtering to deposit the top metal. As Ti is a good metal for contacting CNT19, first sputter 100 nm of Ti, followed by 2 &#181;m of Al (1% Si) without breaking the vacuum.</li>
	<li>Coat the wafer with 3.1 &#181;m of positive photoresist with higher viscosity, starting with a 90 sec HMDS treatment at 130 &#176;C, followed by cooling of the wafer on a cold plate, spin-coating at 3,000 rpm, and a 90 sec soft bake at 95 &#176;C.</li>
	<li>Using a photo-lithography mask and exposure tool expose the top metal pattern aligned to the alignment markers, exposure dose 420 mJ/cm2, focus of -1.</li>
	<li>Perform a single puddle development process. This starts with a 90 sec 115 &#176;C post-exposure bake, followed by 60 sec development using developer and 90 sec hard bake at 100 &#176;C.</li>
	<li>Use a microscope to inspect if the lines in the resist are of the correct dimensions and if the overlay to the markers is correct.</li>
	<li>Etch the Ti/Al stack using chlorine plasma etching. For example using an inductive coupled plasma: 30/40 sccm Cl2/HBr, 5 mTorr, 40/500 W Platen/ICP RF power with endpoint detection and 80% overetch using 15/30 sccm Cl2/HBr.</li>
	<li>Use an oxygen plasma stripper to remove the photoresist (1 kW, 400 sccm O2 with endpoint detection and 2 min overetch). If the metal coverage is not complete (i.e., there are pinholes around the CNT) use an organic solvent (e.g., NMP) to remove the photoresist in order to prevent plasma damage to the CNT.</li>
	<li>Clean the wafers. Put them for 10 min in 99% HNO3, followed by rinsing with DI water till the resistivity of the water is 5 M&#937; (organic clean). Use a rinser dryer to dry the wafers.</li>
</ol>
5. Measurements
<ol>
	<li>Use a scanning electron microscope according to manufacturer&#39;s instructions to check the top metallization of the wafers. 
	Note: If necessary the wafer can be mechanically cleaved in order to check the complete CNT via using a sample tilt of 90&#176;, resulting in images as shown in Figure 3. As the samples are electrically conductive no additional treatment steps have to be used and the samples can be directly mounted into the SEM. Generally, high acceleration voltages of 15 or 20 kV can be used, but if the SiO2 layer is charging up too much this can be reduced to 5 kV.</li>
	<li>Perform 4-point probe I-V measurements using a probe station in combination with a semiconductor parameter analyzer as described in Figure 1 and in Vollebregt et al. 16. 
	Note: Normally a voltage sweep from -0.5 to 0.5 V is sufficient, as the potential drop over an interconnect ideally is small. By using a 4-point probe setup the contact resistance of the probe needles and the wire resistances of the setup are omitted.</li>
</ol>

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<li>Pop, E., Mann, D., Wang, Q., Goodson, K., Dai, H. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Thermal+Conductance+of+an+Individual+Single-Wall+Carbon+Nanotube+above+Room+Temperature%5BTitle%5D)+AND+%22Nano+Lett%22%5BJournal%5D)">Thermal Conductance of an Individual Single-Wall Carbon Nanotube above Room Temperature.</a> Nano Lett. 6 (1), 96-100 (2006).</li>
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<li>Choi, Y. -M., et al. Integration and Electrical Properties of Carbon Nanotube Array for Interconnect Applications. Proceedings of the Sixth IEEE Conference on Nanotechnology. , 262-265 (2006).</li>
<li>Dijon, J., et al. Ultra-high density Carbon Nanotubes on Al-Cu for advanced Vias. Technical digest of the IEEE International Electron Devices Meeting. , 33-34 (2010).</li>
<li>Kreupl, F., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Carbon+nanotubes+in+interconnect+applications%5BTitle%5D)+AND+%22Microelectron.+Eng%22%5BJournal%5D)">Carbon nanotubes in interconnect applications.</a> Microelectron. Eng. 64 (1-4), 399-408 (2002).</li>
<li>Vereecke, B., et al. Characterization of carbon nanotube based vertical interconnects. Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials. , 648-649 (2012).</li>
<li>Vollebregt, S., Ishihara, R., Derakhshandeh, J., vander Cingel, J., Schellevis, H., Beenakker, C. I. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Integrating+low+temperature+aligned+carbon+nanotubes+as+vertical+interconnects+in+Si+technology%5BTitle%5D)+AND+%22Proceedings+of+the+11th+IEEE+Conference+on+Nanotechnology%22%5BJournal%5D)">Integrating low temperature aligned carbon nanotubes as vertical interconnects in Si technology.</a> Proceedings of the 11th IEEE Conference on Nanotechnology. , 985-990 (2011).</li>
<li>Yokoyama, D., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Electrical+Properties+of+Carbon+Nanotubes+Grown+at+a+Low+Temperature+for+Use+as+Interconnects%5BTitle%5D)+AND+%22Jpn+J.+App.+Phys%22%5BJournal%5D)">Electrical Properties of Carbon Nanotubes Grown at a Low Temperature for Use as Interconnects.</a> Jpn J. App. Phys. 47 (4), 1985-1990 (2008).</li>
<li>Van der Veen, M. H., et al. Electrical Improvement of CNT Contacts with Cu Damascene Top Metallization. Proceedings of the IEEE International Interconnect Technology Conference. , 193-195 (2013).</li>
<li>Istratov, A. A., Hieslmair, H., Weber, E. R. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Iron+contamination+in+silicon+technology%5BTitle%5D)+AND+%22Appl.+Phys.+A%22%5BJournal%5D)">Iron contamination in silicon technology.</a> Appl. Phys. A. 70, 489-534 (2000).</li>
<li>Vollebregt, S., Tichelaar, F. D., Schellevis, H., Beenakker, C. I. M., Ishihara, R. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Carbon+nanotube+vertical+interconnects+fabricated+at+temperatures+as+low+as+350+%C2%B0C%5BTitle%5D)+AND+%22%22%5BJournal%5D)">Carbon nanotube vertical interconnects fabricated at temperatures as low as 350 °C.</a> 71, 249-256 (2014).</li>
<li>Kikkawa, T., Inoue, K., Imai, K. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Cobalt+silicide+technology%5BTitle%5D)+AND+%22Silicide+Technology+for+Integrated+Circuits%22%5BJournal%5D)">Cobalt silicide technology.</a> Silicide Technology for Integrated Circuits. , The Institution of Engineering and Technology. 77-94 (2004).</li>
<li>Vollebregt, S., Ishihara, R., Tichelaar, F. D., Hou, Y., Beenakker, C. I. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Influence+of+the+growth+temperature+on+the+first+and+second-order+Raman+band+ratios+and+widths+of+carbon+nanotubes+and+fibers%5BTitle%5D)+AND+%22Carbon%22%5BJournal%5D)">Influence of the growth temperature on the first and second-order Raman band ratios and widths of carbon nanotubes and fibers.</a> Carbon. 50 (10), 3542-3554 (2012).</li>
<li>Lim, S. C., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Contact+resistance+between+metal+and+carbon+nanotube+interconnects%3A+Effect+of+work+function+and+wettability%5BTitle%5D)+AND+%22Appl.+Phys.+Lett%22%5BJournal%5D)">Contact resistance between metal and carbon nanotube interconnects: Effect of work function and wettability.</a> Appl. Phys. Lett. 95 (26), 264103(2009).</li>
<li>Ferrari, A. C., Robertson, J. Interpretation of Raman spectra of disordered and amorphous carbon. Phys. Rev. B. 61 (20), 14095-14107 (2000).</li>
<li>Awano, Y., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Carbon+nanotube+via+interconnect+technologies%3A+size-classified+catalyst+nanoparticles+and+low-resistance+ohmic+contact+formation%5BTitle%5D)+AND+%22Phys.+Status+Solidi+%28a%29%22%5BJournal%5D)">Carbon nanotube via interconnect technologies: size-classified catalyst nanoparticles and low-resistance ohmic contact formation.</a> Phys. Status Solidi (a). 203 (14), 3611-3616 (2006).</li>
<li>Van der Veen, M. H., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Electrical+characterization+of+CNT+contacts+with+Cu+Damascene+top+contact%5BTitle%5D)+AND+%22Microelectron.+Eng%22%5BJournal%5D)">Electrical characterization of CNT contacts with Cu Damascene top contact.</a> Microelectron. Eng. 106, 106-111 (2012).</li>
<li>Horibe, M., Nihei, M., Kondo, D., Kawabata, A., Awano, Y. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Mechanical+Polishing+Technique+for+Carbon+Nanotube+Interconnects+in+ULSIs%5BTitle%5D)+AND+%22Jpn+J.+App.+Phys%22%5BJournal%5D)">Mechanical Polishing Technique for Carbon Nanotube Interconnects in ULSIs.</a> Jpn J. App. Phys. 43 (9A), 6499-6502 (2004).</li>
<li>Vollebregt, S., Chiaramonti, A. N., Ishihara, R., Schellevis, H., Beenakker, C. I. M. Contact resistance of low-temperature carbon nanotube vertical interconnects. Proceedings of the 12th IEEE Conference on Nanotechnology. , 424-428 (2012).</li>
<li>Fiorentino, G., Vollebregt, S., Tichelaar, F. D., Ishihara, R., Sarro, P. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/pubmed?term=((Impact+of+the+atomic+layer+deposition+precursors+diffusion+on+solid-state+carbon+nanotube+based+supercapacitors+performances%5BTitle%5D)+AND+%22Nanotechnology%22%5BJournal%5D)">Impact of the atomic layer deposition precursors diffusion on solid-state carbon nanotube based supercapacitors performances.</a> Nanotechnology. 26 (6), 064002(2015).</li>
</ol>

The authors have nothing to disclose.

Figure 1 displays a schematic overview of the structure fabricated in this work, and which was used for the 4-point probe measurements. As the potential is measured through probes carrying no current, the exact potential drop (VH-VL) over the central CNT bundle and its contacts to the metal can be measured. Bigger diameter CNT bundles are used to contact the bottom TiN layer from the contact pads, in order to reduce the total resistance for the current forcing probes and maximize th...

Copper and tungsten, the metals which are currently used for the interconnects in state-of-the-art very-large-scale integration (VLSI) technology, are approaching their physical limits in terms of reliability and electrical conductivity1. While down-scaling transistors generally improves their performance, it actually increases the resistance and current density of the interconnects. This resulted in interconnects dominating the integrated circuit (IC) performance in terms of delay and power consumption2.
Carbon nanotubes (CNT) have been suggested as alternative for Cu and W metallization, especially for vertical interconnects (vias) as CNT can easily been grown vertical3. CNT have been shown to have excellent electrical reliability, allowing an up to 1,000 times higher current density than Cu4. Moreover, CNT do not suffer from surface and grain boundary scattering, which is increasing the resistivity of Cu at the nanometer scale5. Finally, CNT have been shown to be excellent thermal conductors6, which can aid in the thermal management in VLSI chips.
For successful integration of CNT in VLSI technology it is important that the growth processes for the CNT is made compatible with semiconductor fabrication. This requires the low temperature growth of CNT (&#60; 400 &#176;C) using materials and equipment which are considered compatible and scalable to large scale manufacturing. While many examples of CNT test vias have been demonstrated in the literature7,8,9,10,11,12,13,14, most of these use Fe as catalyst which is regarded as a contaminant in IC manufacturing15. Besides, the growth temperature used in many of these works is much higher than the upper limit of 400 &#176;C. Preferably CNT should even be grown below 350 &#176;C, in order to allow integration with modern low-&#954; dielectrics or flexible substrates.
Here we present a scalable method for growing CNT at temperatures as low as 350 &#176;C using Co as catalyst16. This method is of interest for fabricating different electrical structures consisting of vertically aligned CNT in integrated circuits, ranging from interconnect and electrodes to super capacitors and field emission devices. The Co catalyst metal is often used in IC manufacturing for the fabrication of silicide&#8217;s17, while TiN is an often used barrier material7. Moreover, we demonstrate a process for fabricating CNT test vias while only using techniques from standard semiconductor manufacturing. With this, CNT test vias are fabricated, inspected by scanning electron microscopy (SEM) and Raman spectroscopy, and electrically characterized.

<table><tbody><tr><td>Si (100) wafer 4&quot;</td><td>International Wafer Service</td><td></td><td>Resisitivity: 2-5 m&amp;Omega;-cm, thickness: 525 &amp;micro;m&amp;nbsp;</td></tr><tr><td>Ti-sputter target (99.995% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Al (1% Si)-sputter target (99.999% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Co (99.95% purity)</td><td>Kurt J. Lesker</td><td></td><td></td></tr><tr><td>SPR3012 positive photoresist</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>MF-322 developer</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (99.9%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (69.5%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HF 0.55%</td><td>Honeywell</td><td></td><td></td></tr><tr><td>Tetrahydrofuran</td><td>JT Baker</td><td></td><td></td></tr><tr><td>Acetone</td><td>Sigma-Aldrich</td><td></td><td></td></tr><tr><td>ECI3027 positive photoresist</td><td>AZ</td><td></td><td></td></tr><tr><td>Tetraethyl orthosilicate (TEOS)</td><td>Praxair</td><td></td><td></td></tr><tr><td>N&lt;sub&gt;2&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>O&lt;sub&gt;2&lt;/sub&gt; (99.9999%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CF&lt;sub&gt;4&lt;/sub&gt; (99.9970%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Cl&lt;sub&gt;2&lt;/sub&gt; (99.9900%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>HBr (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Ar (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;F&lt;sub&gt;6&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CHF&lt;sub&gt;3&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>H&lt;sub&gt;2&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;H&lt;sub&gt;2&lt;/sub&gt; (99.6000%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>EVG 120 coater/developer</td><td>EVG</td><td></td><td></td></tr><tr><td>ASML PAS5500/80 waferstepper</td><td>ASML</td><td></td><td></td></tr><tr><td>SPTS &amp;Omega;mega 201 plasma etcher</td><td>SPTS</td><td></td><td>Used for Si and metal etching</td></tr><tr><td>SPTS &amp;Sigma;igma sputter coater</td><td>SPTS</td><td></td><td></td></tr><tr><td>Novellus Concept One PECVD</td><td>LAM</td><td></td><td></td></tr><tr><td>Drytek 384T plasma etcher</td><td>LAM</td><td></td><td>Used for oxide etching</td></tr><tr><td>CHA Solution e-beam evaporator</td><td>CHA</td><td></td><td></td></tr><tr><td>AIXTRON BlackMagic Pro CVD tool</td><td>AIXTRON</td><td></td><td>Carbon nanotube growth</td></tr><tr><td>Philips XL50 scanning electron microscope</td><td>FEI</td><td></td><td></td></tr><tr><td>Tepla 300</td><td>PVA TePla</td><td></td><td>Resist plasma stripper</td></tr><tr><td>Avenger rinser dryer</td><td>Microporcess Technologies</td><td></td><td></td></tr><tr><td>Leitz MPV-SP reflecometer</td><td>Leitz</td><td></td><td></td></tr><tr><td>Renishaw inVia Raman spectroscope</td><td>Renishaw</td><td></td><td></td></tr><tr><td>Agilent 4156C parameter spectrum analyzer</td><td>Agilent</td><td></td><td></td></tr><tr><td>Cascade Microtech probe station</td><td>Cascade Microtech</td><td></td><td></td></tr></tbody></table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

The design of the measurement structure used in this work can be found in Figure 1. By employing such a structure the measurement of the CNT bundle resistance and the metal-CNT contact resistances can be determined accurately, as probe and wire resistances are circumvented. The resistance of the bundle is a measure for the quality and density of the CNT bundle. In order to determine the contact resistance bundles of different lengths should be measured.
A typical SEM image of ...

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

The overall goal of this process is to grow vertically aligned carbon nanotubes and manufacture electrical test structures using standard semiconductor techniques. This method can answer key questions in the micro xray field, such as can vertically aligned carbon nano tubes be used for interconnects and other applications in the integrated circuits? The main advantage of this technology is that it's compatible with standard semiconductor fabrication and it has a sufficiently low fabrication temperature that allows integration into the CMOs backend and with certain polymers.To begin this procedure, deposit the bottom metal layer of the test using magnetron sputtering. Perform titanium sputtering using a pure titanium target with argonne plasma at a substrate temperature of 350 degrees Celsius for titanium nitride. Reactive sputtering.Use a combination of argonne and nitrogen at a 350 degrees Celsius substrate temperature using plasma enhanced chemical vapor deposition deposit A one micrometer thick layer of silicon dioxide. When finished, check the thickness of the silicon dioxide layer using a reflectometer next coat, the wafer with 1.4 micrometers of positive photo resist by performing a 92nd dexamethazone treatment at 130 degrees Celsius after cooling the wafer on a cold plate spin coat at 3, 500 RPM. Then soft bake the wafer for 90 seconds at 95 degrees using a photolithography mask and exposure tool.Expose the desired pattern of openings to an exposure dose of 140 millijoules per centimeters squared. Following this, perform a single puddle development process starting with a 92nd 115 degree Celsius post-exposure Bake. Then perform a 62nd development using developer after hard baking at 100 degrees Celsius for 90 seconds.Use a microscope to inspect if the openings in the resist are of the correct dimensions, and if the overlay to the alignment markers is correct. Next plasma etch the contact openings in the silicon dioxide using a triad plasma etcher. It is very important that the titanium nitrite is not exposed to a plasma, otherwise it'll prevent successful growth of the carbon ubes.Remove the sacrificial titanium layer by wet etching in 0.55%of hydrogen fluoride for 60 seconds. After etching, rinse the wafers with deionized water until the water resistivity is five mega ohms. Then dry the wafers using a rinser dryer.At this point, evaporate five nanometers of cobalt using an e-beam evaporator after pumping down to at least two times 10 to the minus six tor. Heat the wafers to 60 degrees Celsius using lamps under vacuum before depositing to remove any water film. To remove the cobalt outside the contact openings by liftoff.Place the wafer in an ultrasonic bath containing tetra hydro Uran for 15 minutes at 35 degrees Celsius. When finished, rinse with deionized water for five minutes and dry using a spinner. Inspect the wafer underneath a microscope and check for resist residues.Optionally, use a special soft cotton swab for liftoff purposes to manually wipe away residues. If residues remain. Perform a longer ultrasonic treatment in tetra hid ferran furan.Following this. Perform carbon nano tube or CNT growth using low pressure chemical vapor deposition. Then cool down the reactor and purge using nitrogen.Use a scanning electron microscope or SEM to check the height of the CNT inside the openings under 45 degree tilt. Then inspect the samples using ramen spectroscopy to determine the crystallinity of the CNT. Use magnetron sputtering to sputter 100 nanometers of titanium followed by two micrometers of aluminum without breaking the vacuum.Next coat the wafer with 3.1 micrometers of positive photoresist with higher viscosity, starting with a 92nd hexa ethyl dilane treatment at 130 degrees Celsius once the wafer has been cooled on a cold plate spin coat at 3000 RPM after soft baking at 95 degrees Celsius for 90 seconds, expose the top metal pattern to an exposure dose of 420 millijoules per centimeter squared with a focus of minus one. Using a photolithography mask and exposure tool. Perform a single puddle development process starting with a 92nd 115 degrees Celsius post-exposure bake.Then perform a 62nd development using developer after hard baking at 100 degrees Celsius for 90 seconds. Use a microscope to inspect if the lines in the resist are of the correct dimensions, and if the overlay to the markers is correct. Following this.Etch the titanium aluminum stack using chlorine plasma etching with an inductive coupled plasma to remove the photo resist. Use an oxygen plasma stripper if the metal coverage is not complete. Use an organic solvent such as nm methyl perone to remove the photo resist.In order to prevent plasma damage to the CNT. Clean the wafers by placing them in 99%nitric acid for 10 minutes. Rinse with deionized water until the resistivity of the wafer is five mega ohms.Finally, dry the wafers with the rinser dryer. A typical SEM image of CNT before metalization is shown here and is useful for checking if the growth time is correctly set in order to obtain the same length as the thickness of the silicon dioxide layer. A cross section inspected by SEM of the same wafer after metalization is shown here and can be used to determine the alignment of the CNT their density.And if a high resolution SEM is used to determine their diameter, the contact area between the CNT and the metal layers can also be investigated. Ramen spectra of cobalt grown CNT at 350 degrees Celsius are displayed here and can be used to investigate the crystallinity and optimize the CNT growth parameters in order to obtain the highest quality CNT IV measurements were performed using four point probe structures. When the IV behavior is linear, it indicates omic contact between the CNT and the metal contacts.From the resistance and the dimension of the bundles, the resistivity can be calculated and compared to the literature After its development. This technique paved the way for researchers in microelectronics to explore the application of vertically lined carbon nanotubes in integrated circuits. After watching this video, you should have a good understanding of how to grow vertically aligned carbon non tubes using chemical vapor depositions into openings for the vertical interconnects.

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Research

JoVE Journal

Engineering

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Learn to fabricate low-temperature carbon nanotube vertical interconnects using standard semiconductor techniques. This method enables integration of vertically aligned CNTs into integrated circuits for advanced electronics applications.

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

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