Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

The overall goal of this process is to grow vertically aligned carbon nanotubes and manufacture electrical test structures using standard semiconductor techniques. This method can answer key questions in the micro xray field, such as can vertically aligned carbon nano tubes be used for interconnects and other applications in the integrated circuits? The main advantage of this technology is that it's compatible with standard semiconductor fabrication and it has a sufficiently low fabrication temperature that allows integration into the CMOs backend and with certain polymers.

To begin this procedure, deposit the bottom metal layer of the test using magnetron sputtering. Perform titanium sputtering using a pure titanium target with argonne plasma at a substrate temperature of 350 degrees Celsius for titanium nitride. Reactive sputtering.

Use a combination of argonne and nitrogen at a 350 degrees Celsius substrate temperature using plasma enhanced chemical vapor deposition deposit A one micrometer thick layer of silicon dioxide. When finished, check the thickness of the silicon dioxide layer using a reflectometer next coat, the wafer with 1.4 micrometers of positive photo resist by performing a 92nd dexamethazone treatment at 130 degrees Celsius after cooling the wafer on a cold plate spin coat at 3, 500 RPM. Then soft bake the wafer for 90 seconds at 95 degrees using a photolithography mask and exposure tool.

Expose the desired pattern of openings to an exposure dose of 140 millijoules per centimeters squared. Following this, perform a single puddle development process starting with a 92nd 115 degree Celsius post-exposure Bake. Then perform a 62nd development using developer after hard baking at 100 degrees Celsius for 90 seconds.

Use a microscope to inspect if the openings in the resist are of the correct dimensions, and if the overlay to the alignment markers is correct. Next plasma etch the contact openings in the silicon dioxide using a triad plasma etcher. It is very important that the titanium nitrite is not exposed to a plasma, otherwise it'll prevent successful growth of the carbon ubes.

Remove the sacrificial titanium layer by wet etching in 0.55%of hydrogen fluoride for 60 seconds. After etching, rinse the wafers with deionized water until the water resistivity is five mega ohms. Then dry the wafers using a rinser dryer.

At this point, evaporate five nanometers of cobalt using an e-beam evaporator after pumping down to at least two times 10 to the minus six tor. Heat the wafers to 60 degrees Celsius using lamps under vacuum before depositing to remove any water film. To remove the cobalt outside the contact openings by liftoff.

Place the wafer in an ultrasonic bath containing tetra hydro Uran for 15 minutes at 35 degrees Celsius. When finished, rinse with deionized water for five minutes and dry using a spinner. Inspect the wafer underneath a microscope and check for resist residues.

Optionally, use a special soft cotton swab for liftoff purposes to manually wipe away residues. If residues remain. Perform a longer ultrasonic treatment in tetra hid ferran furan.

Following this. Perform carbon nano tube or CNT growth using low pressure chemical vapor deposition. Then cool down the reactor and purge using nitrogen.

Use a scanning electron microscope or SEM to check the height of the CNT inside the openings under 45 degree tilt. Then inspect the samples using ramen spectroscopy to determine the crystallinity of the CNT. Use magnetron sputtering to sputter 100 nanometers of titanium followed by two micrometers of aluminum without breaking the vacuum.

Next coat the wafer with 3.1 micrometers of positive photoresist with higher viscosity, starting with a 92nd hexa ethyl dilane treatment at 130 degrees Celsius once the wafer has been cooled on a cold plate spin coat at 3000 RPM after soft baking at 95 degrees Celsius for 90 seconds, expose the top metal pattern to an exposure dose of 420 millijoules per centimeter squared with a focus of minus one. Using a photolithography mask and exposure tool. Perform a single puddle development process starting with a 92nd 115 degrees Celsius post-exposure bake.

Then perform a 62nd development using developer after hard baking at 100 degrees Celsius for 90 seconds. Use a microscope to inspect if the lines in the resist are of the correct dimensions, and if the overlay to the markers is correct. Following this.

Etch the titanium aluminum stack using chlorine plasma etching with an inductive coupled plasma to remove the photo resist. Use an oxygen plasma stripper if the metal coverage is not complete. Use an organic solvent such as nm methyl perone to remove the photo resist.

In order to prevent plasma damage to the CNT. Clean the wafers by placing them in 99%nitric acid for 10 minutes. Rinse with deionized water until the resistivity of the wafer is five mega ohms.

Finally, dry the wafers with the rinser dryer. A typical SEM image of CNT before metalization is shown here and is useful for checking if the growth time is correctly set in order to obtain the same length as the thickness of the silicon dioxide layer. A cross section inspected by SEM of the same wafer after metalization is shown here and can be used to determine the alignment of the CNT their density.

And if a high resolution SEM is used to determine their diameter, the contact area between the CNT and the metal layers can also be investigated. Ramen spectra of cobalt grown CNT at 350 degrees Celsius are displayed here and can be used to investigate the crystallinity and optimize the CNT growth parameters in order to obtain the highest quality CNT IV measurements were performed using four point probe structures. When the IV behavior is linear, it indicates omic contact between the CNT and the metal contacts.

From the resistance and the dimension of the bundles, the resistivity can be calculated and compared to the literature After its development. This technique paved the way for researchers in microelectronics to explore the application of vertically lined carbon nanotubes in integrated circuits. After watching this video, you should have a good understanding of how to grow vertically aligned carbon non tubes using chemical vapor depositions into openings for the vertical interconnects.