A subscription to JoVE is required to view this content. Sign in or start your free trial.

Method Article

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

15K views

⸱

DOI:

10.3791/52711

⸱

July 24th, 2015

 ,  ,  ,  ,  ,  ,  ,  ,  ,  ,  ,  ,  ,  ,  , 
1Department of Physics, University of California at Berkeley, 2Department of Chemistry, University of California at Berkeley, 3Department of Chemical and Biomolecular Engineering, University of California at Berkeley, 4National Institute for Materials Science (Japan), 5Materials Sciences Division, Lawrence Berkeley National Laboratory, 6Kavli Energy NanoSciences Institute, University of California at Berkeley and Lawrence Berkeley National Laboratory

In This Article

Summary

This paper details the fabrication process of a gate-tunable graphene device, decorated with Coulomb impurities for scanning tunneling microscopy studies. Mapping the spatially dependent electronic structure of graphene in the presence of charged impurities unveils the unique behavior of its relativistic charge carriers in response to a local Coulomb potential.

Abstract

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees of freedom to control electronic devices. In particular, the behavior of graphene’s charge carriers in response to potentials from charged Coulomb impurities is predicted to differ significantly from that of most materials. Scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) can provide detailed information on both the spatial and energy dependence of graphene's electronic structure in the presence of a charged impurity. The design of a hybrid impurity-graphene device, fabricated using controlled deposition of impurities onto a back-gated graphene surface, has enabled several novel methods for controllably tuning graphene’s electronic properties.1-8 Electrostatic gating enables control of the charge carrier density in graphene and the ability to reversibly tune the charge2 and/or molecular5 states of an impurity. This paper outlines the process of fabricating a gate-tunable graphene device decorated with individual Coulomb impurities for combined STM/STS studies.2-5 These studies provide valuable insights into the underlying physics, as well as signposts for designing hybrid graphene devices.

Introduction

Graphene is a two-dimensional material with a unique linear band structure, which gives rise to its exceptional electrical, optical, and mechanical properties.1,9-16 Its low-energy charge carriers are described as relativistic, massless Dirac fermions15, whose behavior differs significantly from that of non-relativistic charge carriers in traditional systems.15-18 Controlled deposition of a variety of impurities onto graphene provides a simple yet versatile platform for experimental studies of the response of these relativistic charge carriers to a range of perturbations. Investigations of such systems reveal that graphene impurities can shift the chemical potential6,7, alter the effective dielectric constant8, and potentially lead to electronically mediated superconductivity9. Many of these studies6-8 employ electrostatic gating as a means to tuning the properties of the hybrid impurity-graphene device. Electrostatic gating can shift the electronic structure of a material with respect to its Fermi level without hysteresis.2-5 Moreover, by tuning the charge2 or molecular5 states of such impurities, electrostatic gating can reversibly modify the properties of a hybrid impurity-graphene device.

Back-gating a graphene device provides an ideal system for investigation by scanning tunneling microscopy (STM). A scanning tunneling microscope consists of a sharp metal tip held a few angstroms away from a conductive surface. By applying a bias between the tip and the surface, electrons tunnel between the two. In the most common mode, constant current mode, one can map the topography of the sample surface by raster-scanning the tip back and forth. Additionally, the local electronic structure of the sample can be studied by examining a differential conductance dI/dV spectrum, which is proportional to local density of states (LDOS). This measurement is often termed scanning tunneling spectroscopy (STS). By separately controlling the bias and back-gate voltages, the response of graphene to impurities can be studied by analyzing the behavior of these dI/dV spectra.2-5

In this report, the fabrication of a back-gated graphene device decorated with Coulomb impurities (e.g., charged Ca atoms) is outlined. The device consists of elements in the following order (from top to bottom): calcium adatoms and clusters, graphene, hexagonal boron nitride (h-BN), silicon dioxide (SiO2), and bulk silicon (Figure 1). h-BN is an insulating thin film, which provides an atomically flat and electrically homogeneous substrate for the graphene.19-21 h-BN and SiO2 act as dielectrics, and bulk Si serves as the back-gate.

To fabricate the device, graphene is first grown on an electrochemically polished Cu foil22,23, which acts as a clean catalytic surface for the chemical vapor deposition (CVD)22-25 of graphene. In a CVD growth, methane (CH4) and hydrogen (H2) precursor gases undergo pyrolysis to form domains of graphene crystals on the Cu foil. These domains grow and eventually merge together, forming a polycrystalline graphene sheet.25 The resulting graphene is transferred onto the target substrate, an h-BN/SiO2 chip (prepared by mechanical exfoliation19-21 of h-BN onto an SiO2/Si(100) chip), via poly(methyl methacrylate) (PMMA) transfer.26-28 In the PMMA transfer, the graphene on Cu is first spin-coated with a layer of PMMA. The PMMA/graphene/Cu sample then floats on an etchant solution (e.g., FeCl3 (aq)28), which etches away the Cu. The unreacted PMMA/graphene sample is fished with an h-BN/SiO2 chip and subsequently cleaned in an organic solvent (e.g., CH2Cl2) and Ar/H2 environment29,30 to remove the PMMA layer. The resulting graphene/h-BN/SiO2/Si sample is then wire-bonded to electrical contacts on an ultra-high-vacuum (UHV) sample plate and annealed in an UHV chamber. Finally, the graphene device is deposited in situ with Coulomb impurities (e.g., charged Ca atoms) and studied by STM.2-5

Access restricted. Please log in or start a trial to view this content.

Protocol

1. Electrochemical Polishing of a Cu Foil22,23

Note: Electrochemical polishing exposes bare Cu surface for graphene growth by removing the protective surface coating and controls the growth seed density.

  1. Prepare an electrochemical polishing solution by mixing 100 ml ultra-pure water, 50 ml ethanol, 50 ml phosphoric acid, 10 ml isopropanol, and 1 g urea.
  2. Cut Cu foil into multiple 3 cm by 3 cm foils. Note: Each foil serves as either an anode or a cathode.
  3. Set up the anode/cathode by clipping a Cu foil vertically with a holder and connecting it to the appropriate terminal of the power supply.
    Note: The anode (positive terminal) will be electrochemically polished for graphene growth.
  4. Before the polishing begins, set constant voltage of 4.8 V in the power supply.
  5. Turn on the power supply as soon as the anode and the cathode are simultaneously dipped into the electrochemical polishing solution. Separate the electrodes by about 2 cm. Check that the resulting current is between 1-2 A.
  6. Stop electrochemical polishing after 2 min by turning off the power supply. Take out the anode and immediately rinse it separately with ultra-pure water, acetone, and isopropanol.
  7. Blow-dry the rinsed Cu foil with N2 gas and store it in a dry container.

2. Chemical Vapor Deposition (CVD) of Graphene on a Cu Foil22-25

  1. Place a quartz tube in a CVD furnace and connect the tube to the rest of the gas line with KF fittings.
  2. Place an electrochemically polished Cu foil on top of a quartz boat. Using a long rod, push the quartz boat into the quartz tube until the Cu foil is placed at the center of the CVD furnace. Enclose the system with KF fittings.
  3. Pump down the system with a roughing pump. Purge the system with H2.
  4. Ramp up the temperature to 1,050 °C with 200 sccm of H2. Anneal at 1,050 °C with the same gas flow for 2 hr.
    Note: The temperature is measured via built-in Type K thermocouple in a tube furnace.
  5. Cool down to 1,030 °C with the same gas flow. Grow graphene for 10 min with 40 sccm CH4 and 10 sccm H2.
  6. As soon as the growth is over, open up the furnace hood to cool rapidly down toRT. Keep the same gas flow.
  7. Once the temperature is below 100 °C, turn off the gas flow.
  8. Turn off the pump. Vent the system with N2 gas by slowly opening the metering valve between the gas line and the N2 gas cylinder.
  9. Take out the sample. Cut the Cu foil into pieces with desired dimensions.
  10. Store the sample in a dry container inside a desiccator.

3. Mechanical Exfoliation19-21 of h-BN onto a SiO2 Chip

  1. Clean an SiO2 chip. Note: The SiO2 chip consists of a roughly 285 nm thick SiO2 layer on top of a bulk Si.
    1. Cut a SiO2 wafer into about 1 cm by 1 cm chips using a diamond scribe.
    2. Rinse the SiO2 chip with water and isopropanol. Keep the SiO2 surface covered with water/isopropanol after each rinse.
    3. Place the SiO2 chip on the spin coater to remove liquid from its surface. Spin the chip with 3,000 rpm for 15 sec.
    4. Check the cleanliness of the chip under an optical microscope with dark field setting. Note: Under dark field setting, solid impurities appear as bright particles.
  2. Place a clean SiO2 chip, exfoliation tape, and h-BN crystal on a clean table with an optical microscope.
  3. Prepare two strips of tape: a parent tape and a second tape. Place both on the table with their sticky sides up. Place a h-BN crystal on the sticky side of the parent tape.
  4. Place the sticky side of the second tape over the h-BN crystal on the parent tape (so that sticky sides of the second and parent tapes are touching). Rub over the crystal gently to remove trapped air bubbles.
  5. Peel the second tape off to exfoliate the h-BN crystal onto the second tape. Store the parent tape for future use.
  6. Fold the second tape onto itself, rub gently over the crystal, and peel off the tape. Repeat this process 10 times, folding the second tape so that the h-BN crystals are transferred to a fresh new region of the second tape each time.
  7. Place a clean SiO2 chip under the microscope. Stick the region of the second tape containing the h-BN crystal onto the SiO2 chip. Ensure that the tape also sticks to the microscope stand for securing the chip during the upcoming exfoliation step.
  8. Slowly peel off the tape, monitoring the process under the microscope. As the tape is nearly peeled off, use a tweezer to hold the SiO2 chip in place. Note: Peeling too fast will result in less h-BN flakes on the chip.
  9. Once the tape is peeled off, place the chip inside a CVD furnace. Anneal the chip in air at 500 °C for 2 hr.

4. Poly(methyl methacrylate) (PMMA)26-28 Transfer of Graphene onto h-BN/SiO2

  1. Put one drop of PMMA (A4) on the graphene/Cu/graphene foil. Spin-coat the foil with 3,000 rpm in 30 sec. Note: As FeCl3 (aq) etches away the Cu layer during the upcoming etching step, the backside graphene will fall off while the PMMA/graphene layer will remain unreacted (Figure 2).
  2. Using a FeCl3 resistant spoon, let the spin-coated Cu foil float on the following solutions in this order: 1.5 min on FeCl3 (aq), 5 min on ultra-pure water, 1 min on FeCl3 (aq), 5 min on ultra-pure water, 15 min on FeCl3 (aq), 5 min on ultra-pure water, 5 min on ultra-pure water, and 30 min on ultra-pure water. Prepare each ultra-pure water bath in a separate beaker.
  3. Fish the PMMA/graphene sample with a h-BN/SiO2 chip. Place it on a hot plate at 80 °C for 10 min to remove water and at 180 °C for 15 min to relax27 PMMA film.
  4. Place the PMMA/graphene/h-BN/SiO2 chip in CH2Cl2 O/N to dissolve the PMMA layer.

5. Ar/H2 Annealing29,30

  1. Place the quartz tube on the CVD furnace and connect the tube to the rest of the gas line with KF fittings.
  2. Place the graphene/BN/SiO2 chip on a quartz boat. Using a long rod, push the quartz boat into the quartz tube until the chip is placed at the center of the CVD furnace. Enclose the system with KF fittings.
  3. Pump down the system with a roughing pump. Purge the system with H2 and Ar.
  4. Build up the pressure to 1 atm with 100 sccm H2 and 200 sccm Ar with a metering valve. Once the pressure reaches 1 atm, adjust the aperture size of the metering valve to stabilize the pressure at 1 atm.
  5. Ramp up the temperature to 350 °C and anneal for 5 hr with the same gas flow.
  6. Cool down to RT with the same gas flow.
  7. Once the temperature is below 100 °C, turn off the gas flow. Close all valves.
  8. Turn off the pump. Vent the system with N2 gas by slowly opening the metering valve between the gas line and the N2 gas cylinder.
  9. Take out the sample. Check the number of graphene layers and defect level with Raman spectroscopy32. Check its cleanliness/uniformity under optical microscope. Scan multiple areas that appear clean under the optical microscope with atomic force microscope (AFM) to ensure that the sample appears clean/uniform at a small length scale (<500 nm) as well.
  10. Store it in a dry container inside a desiccator.

6.  Assembling a Gate-tunable Graphene Device for STM Measurement2-5

  1. Evaporate a 50 µm by 50 µm Au/Ti contact pad onto the Ar/H2-annealed CVD graphene/h-BN/SiO2 sample.
    1. Tape the sample onto a stage on top of a micromanipulator.
    2. While monitoring with optical microscope, align a stencil mask with graphene using the micromanipulator so that the Au/Ti contact will be deposited near the region of interest without covering the surface.
    3. Transfer the sample with stencil mask to an e-beam evaporator. Evaporate 10 nm of Ti at 3 Å/sec. Cover up the Ti layer by evaporating 30-50 nm of Au at 3 Å/sec in the same evaporation session without breaking vacuum. Note: Alternatively, 1 nm of Cr is a good substitute for the 10 nm of Ti.
    4. Transfer the sample with stencil mask back to the micromanipulator for removing the stage.
  2. Mount the sample onto an ultra-high-vacuum (UHV) sample plate.
    1. Place a thin piece of sapphire on a UHV sample plate. Note: The sapphire acts as an insulating layer that prevents electrical contact between the Si and STM ground. Furthermore, sapphire is an excellent thermal conductor for the purpose of sample annealing.
    2. Place the sample on top of the sapphire. Place another thin piece of sapphire on the sample. Make sure that the sapphire does not cover the graphene surface.
    3. Secure the sapphire/sample/sapphire structure with a metallic clamp. Ensure that the entire structure is rigid or else it will vibrate inside a STM.
  3. Wire-bond the UHV sample plate terminals to appropriate contacts on the graphene device. Note: The deposited Au/Ti electrodes are wire-bonded to ground while the Si bulk is wire-bonded to the gate electrode (Figure 1).
    1. Place the mounted sample on a grounded wire-bonding stage.
    2. Identify locations of the Au/Ti contacts using an optical microscope.
    3. Turn on a wire-bonder. If the wire-bonder is pneumatic, turn on N2 gas. Set the wire-bonder to make two bonds.
    4. Using a wire-bonding arm, place the tip of the wire bonder on top of the appropriate terminal on the UHV sample plate. Move down and gently press the tip of the wire bonder onto the terminal until the wire-bonder indicates that the bonding is finished.
    5. Thread a wire to the Au/Ti contact on the graphene device. Move down and gently press the tip of the wire bonder onto the Au/Ti contact until the wire-bonder indicates that the bonding is finished.
    6. Use a diamond scribe to scratch off some SiO2 on the edge of the SiO2 chip to expose the Si that will be used as a back-gate. Repeat the two-bonding process for the exposed Si.
    7. Insert the sample inside a UHV (10-10 Torr) prep chamber and anneal the wire-bonded graphene device at around 300 °C. Transfer the device to a STM chamber.
      Note: The graphene device should be annealed until its surface appears clean under STM (see Sec. 8 of the Protocol). The annealing time will vary depending on the initial cleanliness of the device.

7. STM Tip Calibration on Au(111) Surface31

  1. Anneal/sputter an Au(111) sample on the heater stage in a UHV chamber to clean/flatten the Au surface. Anneal for 5 min at 375 °C, and sputter for 5 min with Ar+ beam accelerated to 500 V. Transfer the Au(111) sample to the STM scanning stage.
  2. Approach an Au(111) surface with a STM tip. Apply 10 V pulses on the STM tip until an Au(111) herringbone reconstruction is clearly visible.
  3. Calibrate the tip by adjusting the tip shape and comparing the differential conductance dI/dV spectrum to the standard Au(111) dI/dV spectrum.31
    1. Scan the Au(111) surface with 40 nm by 40 nm frame to identify a clean/flat area. If the surface has a high density of step edges, move to a new area for scanning.
    2. Gently crash the STM tip 0.4 to 1.0 nm into a clean region of the Au(111) surface; this controlled crashing is referred to as a “poke.” Turn off the feedback and click “Take Spectroscopy” button to take a dI/dV spectrum via lock-in onto the current response of an ac modulated voltage (6 mV and 613.7 Hz) added to the tip bias.
      Note: Once ac modulated voltage (6 mV and 613.7 Hz) is provided on the tip, the resulting tunneling current goes into the lock-in amplifier, which isolates the component of the current with the same frequency and returns dI/dV signal. By recording this signal as the sample bias is swept from -1.0 to 1.0 V, dI/dV spectrum is generated. Because this spectroscopy program is home-written, the instruction for taking the spectroscopy will vary among different programs.
    3. Check the obtained dI/dV curve against a standard Au(111) dI/dV spectrum (Figure 4). Make sure the Au(111) surface state is present in the dI/dV curve and that the spectrum is absent of any anomalous feature. If the measured dI/dV curve is not acceptable, repeat the poke in step 7.3.2 until the dI/dV curve looks like the one shown in Figure 4.
    4. Once tip shape and dI/dV spectrum are optimized, wait 15 to 30 min; if the STM tip is unstable, dI/dV spectrum will change during this time interval. Retake a dI/dV spectrum at a different location to confirm whether the STM tip is stable or not.
    5. Repeat the poke in step 7.3.2 if dI/dV curve has changed. Proceed to scan graphene if dI/dV curve is unchanged.

8. Scanning Graphene

  1. Transfer the graphene device to a STM scanning stage.
  2. Use a long-distance optical microscope to see the STM tip and graphene device. After laterally aligning the tip and h-BN flake of interest, approach the graphene.
  3. Start scanning a 2 nm by 2 nm area. Slowly enlarge the scan window to 5 nm by 5 nm, 10 nm, by 10 nm, 15 nm by 15 nm, 20 nm by 20 nm, etc. If a large impurity (>100 pm in height) is encountered, withdraw the tip and move to a different area.
  4. Take a dI/dV spectrum and compare to the standard dI/dV spectrum on graphene/h-BN substrate (see Ref. 21). If the spectrum is not comparable, recalibrate the tip on an Au(111) surface (see Sec. 7 of the Protocol).
  5. Scan multiple areas to get a sense of how frequently large impurity (>100 pm in height) is encountered. Based on these statistics, deduce the cleanliness of the sample.

9. Depositing Coulomb Impurities on a Graphene Surface2-4

  1. Obtain a Ca source. Calibrate the evaporation of Ca atoms with a residual gas analyzer (RGA) and quartz crystal microbalance (QCM) in an UHV test chamber. Note: RGA evaluates the purity of Ca deposit while QCM measures a Ca deposition rate.
    1. Run current through the Ca source.
    2. Increase the current until a Ca partial pressure of 10-10 Torr is detected in the RGA mass spectrum. Be aware of the fact that Ca and Ar have the same mass and therefore are indistinguishable in the RGA.
    3. Measure the Ca deposition rate (layer/sec) with the QCM.
      1. Input the density (e.g., 1.55 g/cm3 for Ca ion) of the deposit to convert frequency shift value to deposition rate.
      2. The deposition rate monitor for the QCM reads the deposition rate in /s; convert this to layer/sec by assuming that the thickness of a monolayer is equal to the ionic diameter (e.g., 0.228 Å for Ca ion) of the deposit. 
    4. Determine the optimal current by adjusting the current until the deposition rate monitor indicates a desired deposition rate (e.g., 3.33 x 10-5 layer/sec). 
  2. Given the deposition rate (e.g., 3.33 x 10-5 layer/sec) in step 9.1.3, calculate the time (sec) for depositing the desired amount (e.g., 0.01 monolayer) of Ca. In the STM, deposit Ca on a Cu(100) surface in situ with the optimal current setting from step 9.1.3. Check the Ca coverage and cleanliness of the post-deposition Cu(100) surface with STM (see step 8.5); recalibrate the current setting until the Cu(100) surface condition under STM appears as expected.
    Note: Deposition parameters are optimized on Cu(100) first to minimize the risk of contaminating the graphene device with poorly controlled deposition.
  3. Transfer the graphene device to a STM for in situ deposition at 4 K.
  4. Deposit charged Ca atoms onto the graphene surface.
    1. Before depositing Ca on graphene, outgass the Ca source. Slowly increase the current on the source by 0.25 A every 5-10 min until the desired current in step 9.2 is reached. Close a shutter between the graphene and Ca source to prevent outgassed contaminants from reaching the graphene.
    2. Let the evaporation flux stabilize for 20 min before opening the shutter.
    3. Open the shutter and deposit desirable (e.g., 0.01 monolayer) amount of Ca ions onto the graphene surface. Ensure that the graphene device has line-of-sight with the Ca source. Ensure that the STM tip is out of line-of-sight of the Ca source to prevent Ca atoms from sticking to the STM tip.
  5. Check the Ca coverage and cleanliness of the post-deposition graphene surface with STM (see Step 8.5). Refer to Ref. 2, 3, and 4 for further protocol of the study of Coulomb impurities on graphene.

Access restricted. Please log in or start a trial to view this content.

Results

Figure 1 illustrates a schematic of a back-gated graphene device. Wire-bonding Au/Ti contact to an UHV sample plate grounds graphene electrically, while wire-bonding Si bulk to an electrode that connects to an external circuit back-gates the device. By back-gating a device, a charge state of a Coulomb impurity at a given sample bias (which is controlled by the STM tip) can be tuned to a different charge state.2-4

Figure 2 outlines the steps for fabr...

Access restricted. Please log in or start a trial to view this content.

Discussion

For STM characterization, critical goals of the graphene device fabrication include: 1) growing monolayer graphene with a minimal number of defects, 2) obtaining a large, clean, uniform, and continuous graphene surface, 3) assembling a graphene device with high resistance between the graphene and the gate (i.e., no “gate leakage”), and 4) depositing individual Coulomb impurities.

The first goal is governed by the CVD process, during which graphene grows on a Cu foil. Altho...

Access restricted. Please log in or start a trial to view this content.

Disclosures

Authors have nothing to disclose.

Acknowledgements

Our research was supported by the Director, Office of Science, Office of Basic Energy Sciences of the U.S. Department of Energy sp2 Program under contract no. DE-AC02-05CH11231 (STM instrumentation development and device integration); the Office of Naval Research (device characterization), and NSF award no. CMMI-1235361 (dI/dV imaging). STM data were analyzed and rendered using WSxM software.33 D. W. and A.J.B. were supported by the Department of Defense (DoD) through the National Defense Science & Engineering Graduate Fellowship (NDSEG) Program, 32 CFR 168a.

Access restricted. Please log in or start a trial to view this content.

Materials

List of materials used in this article
NameCompanyCatalog NumberComments
Cu foilAlfa AesarCAS # 7440-50-8
Lot # F22X029
Stock # 13382		99.8% Cu
Scotch Magic TapeScotch®N/Afor exfoliation of hBN
PMMAMicro ChemM23004 0500L 1GLA4
FeCl3 resistant spoonBel-Art ScienceWare367300015PTFE coated double ended chemical spoon, 15 cm length
FeCl3 (aq)Ricca Chemical3127-1640% w/v
SiO2/Si(100) ChipNOVA Electric MaterialsHS39626-OXn/a
h-BNK. Watanabe and T. Taniguchi GroupContact the grouphexagonal Japanese BN (JBN)
Au(111)Agilent TechnologiesN9805B-FGAu(111) epitaxially grown on mica
SapphirePrecision Ferrites & Ceramic, Inc.Contact vendorP/N Sapphire Chips
0.22 x 0.125 x 0.015"
Ca sourceTrace Sciences International Corp.AS-3-Ca-5-Sn/a
Cu(100)Princeton ScientificContact vendorCu(100) single crystal
MethanePraxair, Inc.ME 5.0RS-KGraphene growth precursor gas
HydrogenPraxair, Inc.HY 6.0RS-KGraphene growth precursor gas

References

  1. Novoselov, K. S., et al. Electric field effect in atomically thin carbon films. Science. 306 (5696), 666-669 (2004).
  2. Brar, V. W., et al. Gate-controlled ionization and screening of cobalt adatoms on a graphene surface. Nat. Phys. 7 (1), 43-47 (2011).
  3. Wang, Y., et al. Mapping Dirac quasiparticles near a single Coulomb impurity on graphene. Nat. Phys. 8 (9), 653-657 (2012).
  4. Wang, Y., et al. Observing atomic collapse resonances in artificial nuclei on graphene. Science. 340 (6133), 734-737 (2013).
  5. Riss, A., et al. Imaging and tuning molecular levels at the surface of a gated graphene device. ACS Nano. 8 (6), 5395-5401 (2014).
  6. Chen, J. H., Jang, C., Adam, S., Fuhrer, M. S., Williams, E. D., Ishigami, M. Charged-impurity scattering in graphene. Nat. Phys. 4 (5), 377-381 (2008).
  7. Pi, K., et al. Electronic doping and scattering by transition metals on graphene. Phys. Rev. B. 80 (7), 075406(2009).
  8. Jang, C., et al. Tuning the effective fine structure constant in graphene: Opposing effects of dielectric screening on short- and long-range potential scattering. Phys. Rev. Lett. 101 (14), 146805(2008).
  9. McChesney, J. L., et al. Extended van Hove singularity and superconducting instability in doped graphene. Phys. Rev. Lett. 104 (13), 136803(2010).
  10. Geim, A. K., Novoselov, K. S. The rise of graphene. Nat. Mater. 6 (3), 183-191 (2007).
  11. Wang, F., et al. Gate-variable optical transitions in graphene. Science. 320 (5873), 206-209 (2008).
  12. Lee, C., Wei, X. D., Kysar, J. W., Hone, J. Measurement of the elastic properties and intrinsic strength of monolayer graphene. Science. 321 (5887), 385-388 (2008).
  13. Zhang, Y., et al. Giant phonon-induced conductance in scanning tunneling spectroscopy of gate-tunable graphene. Nat. Phys. 4 (8), 627-630 (2008).
  14. Zhang, Y., Tan, Y. W., Stormer, H. L., Kim, P. Experimental observation of the quantum Hall effect and Berry’s phase in graphene. Nature. 438 (7065), 201-204 (2005).
  15. Novoselov, K. S., et al. Two-dimensional gas of massless Dirac fermions in graphene. Nature. 438 (7065), 197-200 (2005).
  16. Biswas, R. R., Sachdev, S., Son, D. T. Coulomb impurity in graphene. Phys. Rev. B. 76 (20), 205122(2007).
  17. Novikov, D. S. Elastic scattering theory and transport in graphene. Phys. Rev. B. 76 (24), 245435(2007).
  18. Pereira, V. M., Nilsson, J., Castro Neto, A. H. Coulomb impurity problem in graphene. Phys. Rev. Lett. 99 (16), 166802(2007).
  19. Dean, C. R., et al. Boron nitride substrates for high-quality graphene electronics. Nat. Nanotechnol. 5 (10), 722-726 (2010).
  20. Xue, J., et al. Scanning tunnelling microscopy and spectroscopy of ultra-flat graphene on hexagonal boron nitride. Nat. Mater. 10 (4), 282-285 (2011).
  21. Decker, R., et al. Local electronic properties of graphene on a BN substrate via scanning tunneling microscopy. Nano Lett. 11 (6), 2291-2295 (2011).
  22. Yan, Z., et al. Toward the synthesis of wafer-scale single-crystal graphene on copper foils. ACS Nano. 6 (10), 9110-9117 (2012).
  23. Zhang, B., et al. Low-temperature chemical vapor deposition growth of graphene from toluene on electropolished copper foils. ACS Nano. 6 (3), 2471-2476 (2012).
  24. Li, X., et al. Large-area synthesis of high-quality and uniform graphene films on copper foils. Science. 324 (5932), 1312-1314 (2009).
  25. Zhang, Y., Zhang, L., Zhou, C. Review of chemical vapor deposition of graphene and related applications. Acc. Chem. Res. 46 (10), 2329-2339 (2013).
  26. Reina, A., et al. Transferring and identification of single-and few-layer graphene on arbitrary substrates. J. Phys. Chem. C. 112 (46), 17741-17744 (2008).
  27. Suk, J. W., et al. Transfer of CVD-grown monolayer graphene onto arbitrary subsrates. ACS Nano. 5 (9), 6916-6924 (2011).
  28. Regan, W., et al. A direct transfer of layer-area graphene. Appl. Phys. Lett. 96 (11), 113102(2010).
  29. Ishigami, M., Chen, J. H., Cullen, W. G., Fuhrer, M. S., Williams, E. D. Atomic structure of graphene on SiO2. Nano Lett. 7 (6), 1643-1648 (2007).
  30. Dan, Y., Lu, Y., Kybert, N. J., Luo, Z., Johnson, A. T. C. Intrinsic response of graphene vapor sensors. Nano Lett. 9 (4), 1472-1475 (2009).
  31. Chen, W., Madhavan, V., Jamneala, T., Crommie, M. F. Scanning tunneling microscopy observation of an electronic superlattice at the surface of clean gold. Phys. Rev. Lett. 80 (7), 1469-1472 (1998).
  32. Saito, R., Hofmann, M., Dresselhaus, G., Jorio, A., Dresselhaus, M. S. Raman spectroscopy of graphene and carbon nanotubes. Adv. Phys. 60 (3), 413-550 (2011).
  33. Horcas, I., Fernandez, R., Gomez-Rodriguez, J. M., Colchero, J., Gomez-Herrero, J., Baro, A. M. WSXM: A software for scanning probe microscopy and a tool for nanotechnology. Rev. Sci. Instrum. 78 (1), 013705(2007).

Access restricted. Please log in or start a trial to view this content.

Reprints and Permissions

Tags

Gate tunable DevicesSTM STS StudiesGraphene GrowthHexagonal Boron NitrideGold Titanium ContactsUltra High VacuumDifferential Conductance
Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
Contact Us
Recommend to Library

Privacy

Terms of Use

Policies

Copyright © 2026 MyJoVE Corporation. All rights reserved.