Since Cu interconnects were firstly introduced into the ultra-large-scale integration (ULSI) technology in 1997 1, low-k and ultra-low-k (ULK) dielectrics have been adopted into the back-end-of-line (BEoL) as the insulating materials between on-chip interconnects. The combination of new materials, e.g., Cu for reduced resistance and low-k/ULK dielectrics for lower capacitance, overcomes the effects of increased resistance-capacitance (RC) delay caused by interconnect dimensional shrinkage 2, 3. However, this benefit was encroached by the continuing aggressive scaling of microelectronic devices in recent years. The use of low-k/ULK materials results in various challenges in the manufacturing process and for the product reliability, particularly if the interconnect pitch reaches about 100 nm or less 4-6.
TDDB refers to the physical failure mechanism of a dielectric material as a function of time under an electric field. The TDDB reliability test is usually carried out under accelerated conditions (elevated electrical field and/or elevated temperature).
The TDDB in on-chip interconnect stacks is one of the most critical failure mechanisms for the microelectronic devices, which has already raised intense concerns in the reliability community. It will continue to be in the spotlight of reliability engineers since ULK dielectrics with even weaker electrical and mechanical properties are being integrated into the devices in advanced technology nodes.
Dedicated experiments have been performed to investigate the TDDB failure mechanism 7-9, and a significant amount of effort has been invested to develop models which describe the relationship between electric field and lifetime of the devices 10-13. The existing studies benefit the community of reliability engineers in microelectronics; however, many challenges still exist and many questions still need to be answered in detail. For example, proven models to describe the physical failure mechanism and degradation kinetics in the TDDB process and the respective experimental verification are still lacking. As a particular need, a more appropriate model is needed to substitute the conservative √E-model 14.
As a very important part of the TDDB investigation, typical failure analysis is facing an unprecedented challenge, i.e., providing comprehensive and hard evidence to explain the physics of failure mechanisms and degradation kinetics. Apparently, inspecting millions of vias and meters of nanoscale Cu lines one by one and ex situ imaging the failure site is not the appropriate choice to hurdle this challenge, because it is very time consuming, and only limited information about the kinetics of the damage mechanism can be provided. Therefore, an urgent task has emerged to develop and to optimize experiments and to get a better procedure to study the TDDB failure mechanisms and degradation kinetics.
In this paper, we will demonstrate an in situ experimental methodology to investigate the TDDB failure mechanism in Cu/ULK interconnect stacks. A TEM with the ability of high quality imaging and chemical analysis is used to study the kinetic process at dedicated test structures. The in situ electrical test is integrated into the TEM experiment to provide an elevated electrical field to the dielectrics. A customized “tip-to-tip” structure, consisting of fully encapsulated Cu interconnects and insulated by a ULK material, is designed in the 32 nm CMOS technology node. The experimental procedure described here can also be extended to other structures in active devices.