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Indium Phosphide Synaptic Device on Silicon to Emulate Synaptic Behavior for Neuromorphic Computing

Debarghya Sarkar*1, Jun Tao*1, Wei Wang1, Qingfeng Lin1, Matthew Yeung1, Chenhao Ren, Rehan Kapadia1
* These authors contributed equally


The protocol presented here describes, in detail, the process flow for a templated liquid-phase growth of crystalline indium phosphide (InP) nanostripes directly on an Si/SiO2 substrate with MoOx as a thin buffer layer. These InP nanostripes are, then, taken to fabricate InP channel field-effect transistors (FETs) in a scalable manner. Notably, this process allows researchers to obtain InP stripes in the exact geometry and location as may be required for scalable device array fabrication. Further, these FETs are utilized to demonstrate artificial synaptic behavior. The occupation of charge traps in the oxide is modulated by applying gate pulses that mimic pre-synaptic action potentials. The variation of the trapped charge density due to the time-correlated activity of the pre- and postsynaptic neurons results in a threshold voltage shift leading to a change in channel conductance, which is interpreted here as the synaptic weight. A temporal variation of the threshold voltage shift and, thus, of the synaptic weight, arises from the relaxation of traps. Utilizing the time and neuronal activity-dependent synaptic weight change, several important non-linear biological synaptic behaviors are mimicked by the artificial synapse.

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