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The Effect of Anodization Parameters on the Aluminum Oxide Dielectric Layer of Thin-Film Transistors
Chapters
Summary May 24th, 2020
Anodization parameters for growth of the aluminum-oxide dielectric layer of zinc-oxide thin-film transistors (TFTs) are varied to determine the effects on the electrical parameter responses. Analysis of variance (ANOVA) is applied to a Plackett-Burman design of experiments (DOE) to determine the manufacturing conditions that result in optimized device performance.
Transcript
Here is the overview of the protocol. We start by preparing the electrolytic solution, mixing water, ethylene glycol, and tartaric acid. After that, the substrate glass slides need to be cleaned by sonication in alkaline detergent solution, acetone and isopropanol followed by RF plasma cleaning.
The construction of the TFT is done by depositing an aluminium electrode onto the clean glass substrates. Followed by anodization into aluminum oxide sputtering of the zinc oxide active layer and thermal evaporation the drain source electrodes. The aluminum anodization process is carried out by submerging the aluminium coated glass substrate and a gold plated, stainless steel sheet connected to a source measure unit.
The process starts by applying constant current in the system with a voltage increasing linearly until the final voltage which determines the oxide thickness. Therefore, the voltage is maintained constant until the current across the system drops to zero. The Electrical characterization of the TFTs is performed by connecting a dual channel source-measuring unit to the gate, drain and source electrodes.
The transfer curve is obtained by varying the gate voltage at a constant drain source voltage and measuring the drain source current. The electrical mobility can be determined from the TFT transfer curve. The Placket-Burman design of experiments is performed by labeling the Anodization factors, whichever ride from a low to a high level, determined from the experimental conditions.
The Placket-Burman matrix is composed by twelve experimental runs, which correspond to different combinations of the Anodization factors in the predetermined levels. We present here in a protocol to build the zinc oxide tin-filled transistors using anodized aluminum oxide as a gate dielectric layer. We show that it's possible to optimize the performance of TFTS by varying only the anodization process parameters of the gate dielectrics.
The electrolytic solution is prepared by mixing 84 mL of ethylene glycol to 1.5 g of tartaric acid. Therefore, add 16 mL of deionized water to the solution, shake gently the solution. After that, stir the solution for approximately 30 minutes until complete dissolution of tartaric acid.
Prepare two stocks solutions from ammonia hydroxide to adjust the pH of the electrolyte. The more concentrated solution can be about 28%and the less concentrated about 2%Make the coarse adjustment of the pH using the more concentrated ammonium hydroxide solution. When the pH is close to the desired value, five or six, use the less concentrated solution to finely adjust the pH.
The Substrate cleaning procedure starts by sonicating the glass substrates in alkaline detergent solution, 5%in volume at 16 degrees Celsius for 50 minutes. After that, the substrates are rinsed abundantly in deionized water to remove any residues. Dry the substrate by blowing with clean, dry air or nitrogen.
The dried substrates are sonicated again in acetone for five minutes. Remove from acetone and dry again in clean dry air or nitrogen. Sonicate once more in isopropanol for five minutes.
Remove from isopropanol and repeat the drying procedure. Load the substrates into a RF plasma cleaner and evacuate the chamber. When vacuum is achieved, turn on the RF at medium power and leave for five minutes to finish the cleaning procedure.
Remove the substrates from the plasma cleaner and load them into a sample holder with appropriate shadow masks for thermal evaporation of the aluminum gate electrode. The shadow mask, is a stainless laser cut sheet which determines the aluminum gate electrode area. Insert the glass slides into the thermal evaporation chamber and start the deposition procedure.
Deposit the aluminum gate electrode with fine control of the evaporation rate and the final thickness of the film. After the evaporation, remove the samples from the chamber. And check if the electrodes were properly deposited.
The anodization of the aluminum gate electrode starts by connecting the aluminum coated glass slide and the gold plated stainless steel sheet to the clip connectors. Therefore, the electrodes are submerged into the electrolytic solution and the cables are connected to the Source-Measure Unit. Apply constant current to the electrodes.
The voltage drop has to increase linearly, demonstrating that the aluminum oxide growth is occurring properly. When the established final voltage is achieved, switch the SMU to constant voltage mode and wait until the current drops to zero. After finishing the anodization procedure, rinse abundantly the substrate in deionized water.
And finish by drying the substrate in dry, clean air or nitrogen. The deposition of the transistor active layer is performed by inserting the substrate with the anodized aluminum oxide layer into appropriate shadow masks. The masks would permit the selective covering of zinc oxide during the sputtering deposition.
Insert the samples into this sputtering chamber and initiate the deposition process. Control the sputtering deposition rate and the final thickness of the TFT active layer. After sputtering deposition, remove the samples from the chamber and prepare them for thermal evaporation of the drain and source electrodes.
The transistor fabrication is concluded by evaporating the aluminum drain and source electrodes by thermal evaporation using appropriate shadow masks. The used mask design allows the fabrication of three transistors in each substrate. Insert the samples into the evaporation chamber and initiate the deposition procedure.
After the evaporation of the aluminum drain and source electrodes, remove the samples from the chamber. Remove the samples from the masks and check the electrodes. The transistors are ready for electrical characterization.
The electrical characterization of the TFT is performed by making the contact to the drain, source and gate electrodes using spring probe connectors. The electrodes are therefore connected to a dual channel source and measure unit. The transistor characteristic curves are obtained by polarizing the drain and source electrodes, as well as the gate electrode and measuring the channel current.
The analysis of the TFT electrical parameters is carried out by plotting the TFT transfer curve and the square root of the drain current as a function of the gate voltage. The slope of the curve permits the determination of the device mobility. The intercept of the slope of the curve with the X-axis defines the TFT threshold voltage.
The analysis of the results obtained the curvature of Placket-Burman design of experiments, can be performed by an analysis software such as Chemoface. Choose the experimental design and enter with the input data. Therefore, calculate the corresponding effects for each anodization parameters and analyze the results by plotting the data in a Pareto chart of effects.
The Pareto chart, allows you to rank the anodization factors by the effect on a specific device response parameter such as the TFT mobility. So Placket-Burman is useful for a number of different reasons. Firstly, it allows you to study a number of different factors, systematically and simultaneously.
And using statistical approaches such as ANOVA and regression, it allows you to quantify and, understand the most significant factors and the least significant factors which are affecting the anodization process. So we think that the Placket-Burman approach is very valuable in printed electronics. It allows you to rapidly and effectively screen a number of different factors and optimize the factors in a very systematic and quick manner.
Although we've developed this approach for anodization, it could be used in many many other areas within printed electronic development.
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