Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Summary

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%^1,2. The resulting geometry allows for measurements of confined liquids and gasses.

Abstract

Measurements of the heat capacity and superfluid fraction of confined ⁴He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments³, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.

Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned² in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water⁴. The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Introduction

When clean silicon wafers are brought into intimate contact at RT, they are attracted to each other via van der Waals forces and form weak local bonds. This bonding can be made much stronger by annealing at higher temperatures^5,6. Bonding can be done successfully with surfaces of either SiO₂ to Si or SiO₂ to SiO₂. Bonding of Si wafers are most commonly used for silicon on insulator devices, silicon-based sensors and actuators, and optical devices⁷. The work described here takes wafer direct bonding in a different direction by using it to achieve well-defined uniformly-spaced enclosures over the entire wafer area^8,9. Having a well-defined geometry where fluid can be introduced allows measurements to be performed in order to determine the effect of the confinement on the properties of the fluid. Hydrodynamic flows can be studied where the small dimension can be controlled from tens of nanometers to several micrometers.

SiO₂ can be grown on Si wafers using a wet or dry thermal oxide process in a furnace. The SiO₂ can then be patterned and etched as desired using lithographic techniques. Patterns which have been used in our work include a pattern of widely spaced support posts which results upon bonding in a planar or film geometry (see Figure 1). We have also patterned channels for one-dimensional characteristics, and arrays of boxes, either of (1 µm)³ or (2 µm)³ dimension¹ (see Figure 2). When designing a confinement with boxes, typically 10-60 million on a wafer, there needs to be a way to fill all of the individual boxes. A separate patterning of the top wafer with a design that stands off the two wafers by 30 nm or more allows for this. Or, equivalently, shallow channels can be designed on the top wafer so that all the boxes are linked. The thickness of the oxide grown on the top wafer is different from that on the bottom wafer. This adds another degree of flexibility and complexity to the design. Being able to pattern both wafers allows for a larger variety of confinement geometries to be realized.

The size of the geometric features in these bonded wafers, or cells, can vary. Cells with planar films as small as 30 nm have been made successfully^10,11. At thicknesses below this, overbonding can take place whereby the wafers bend around the support posts thus "sealing" the cell. Recently, a series of measurements on liquid ⁴He have been performed with an array of (2 µm)³ boxes with varying separation distance between them^10,12. Features much larger in depth than 2 µm are not very practical due to the increasing length of time required to grow the oxide. However, measurements have been made with an oxide as thick as 3.9 µm⁹. The limits on the smallness of the lateral dimension arise from the limits of the lithography capabilities. The limit for the largeness of the lateral dimension is determined by the size of the wafer. We have successfully created planar cells where the lateral dimension spanned almost the entire wafer diameter, but one could just as easily imagine patterning several smaller structures on the order of tens of nanometers in width. However such structures would require e-beam lithography. We have not done this at this time.

In all of our work the bonded wafers formed a vacuum tight enclosure. This is achieved by retaining in the patterned oxide a solid ring of SiO₂ of 3-4 mm in width at the perimeter of the wafer, see Figure 1. This, upon bonding, forms a tight seal. This design could be easily modified if one were interested in hydrodynamic studies which require an input and an output.

The bursting pressure of the bonded cells has also been tested. We found that with 375 µm thick wafers, pressure up to approximately nine atmospheres could be applied. However, we have not studied how this could be improved by bonding over larger oxide areas or, perhaps, for thicker wafers.

The procedure for interfacing the silicon cells to a filling line and the techniques for measuring the properties of the confined helium at low temperature is given in  Mehta et al.² and Gasparini et al.¹³ We note that changes in linear dimension for silicon are only 0.02% upon cooling the cells¹⁴. This is negligible for the patterns formed at RT.

Protocol

1. Before Bonding, Wafer Preparation

This step except for 1.8 is done in the Cornell Nanoscale Facility cleanroom.

1. Grow the oxides in a standard thermal oxidation furnace using a wet oxide process for thick oxides and, to achieve better thickness control, a dry oxide process for very thin oxides. Check the thickness for uniformity over the full wafer with ellipsometry.
2. Create a mask for the geometry you wish to etch.
3. Spin photoresist on the wafers being etched.
4. Expose, develop and bake a test wafer and examine with an appropriate microscope.
5. If the test wafer is exposed as desired, etch the test wafer. The ratio of oxide thickness to lateral feature dimension will determine if a wet or dry etch is appropriate. Since the wet etches are isotropic they will not produce vertical walls in the oxide. In many cases this does not matter. If vertical walls are desired one can use reaction ion etching. If the etching is successful, proceed with the other wafers. Often, the hydrophobic/hydrophilic properties of Si and SiO₂ can be used to see if the etching process has been successful.
6. Remove the photoresist from the wafers. For most photoresists, this can be done initially with isopropyl alcohol and acetone. However, some small amount of resist will still remain on the wafers. This resist needs to be completely removed in order to achieve good bonding.
7. Use a brief 20 min oxygen descumming process in a reactive ion etcher. This will remove whatever photoresist remains on the wafers. However, this will also add some oxide layers to the exposed silicon. This is typically 1-4 nm¹⁵.
8. Drill the filling hole in the top wafer. This can be done with diamond tipped drill bits and smart-cut lubrication (see Materials for manufacturer details). Rinse off the smart-cut immediately after drilling with deionized water. Drilling can also be done using a diamond paste with 3-9 µm grit for filling holes larger than ~0.124 cm in diameter. Smart-cut can again be used for lubrication. We use a small precision drill press at 1,000-2,000 rpm.

2. Bonding Preparation

1. In order to bond wafers, cleanliness is paramount. There are a few steps that should be taken to clean the wafers. First, clean with RCA baths.
   1. Rinse wafers in deionized (DI) water.
   2. Clean in "RCA" acid bath. RCA acid bath is H₂O:H₂O₂:HCl with the ratios of 5:1:1. Place wafers in 80 °C RCA acid for 15 min with the patterned sides facing up. This step will eliminate any metallic contamination.
   3. Remove wafers from the acid and rinse in DI water bath for 5 min.
   4. Clean in the "RCA" base next. RCA base is H₂O:H₂O₂:NH₄OH with the ratios of 10:2:1. Place wafers in 80 °C RCA base for 15 min with the patterned sides facing up. This step will eliminate any organic contamination.
   5. Rinse wafers in DI water bath for ~15 min.
2. The wafers need to be removed from the DI water bath and remain clean in order for proper bonding to occur. This is done in two steps:
   1. First, place the wafers with their patterned etched sides facing each other on a Teflon chuck in a clean microchamber as shown in Figure 3B. They are separated by ~1 mm Teflon tabs. Spray deionized water between the wafers while they spin slowly (~10-60 rpm) for ~2 min in order to remove any particle contamination. A film of water will be left between the wafers at this point. This prevents dust contamination prior to the next step.
   2. Cover the wafers with the clear acrylic lid and spin the wafers dry for ~30 min at 3,000 rpm. Use a 250 W infrared heat lamp to aid the drying process. The rapid spinning will entrain any particle contaminants with the ejection of the water film, as in Figure 3C.
3. Before removing the lid over the wafers, remove the tabs separating the wafers by rotating the lid. This will bring the wafers into light local contact while still in the microclean chamber. Now the wafers may be safely removed from the microclean chamber on their carrier. The very small gap of approximately 1 µm between the wafers will minimize dust contamination during this step. Also, do not pick up the wafers with tweezers at this point since this would initiate asymmetric bonding. Instead, transport the wafers with the use of the removable carrier onto the arbor press.

3. Wafer Bonding

1. Press the two wafers together using an arbor press and a fairly rigid and smooth (Nerf) ball. The Nerf ball is used to apply pressure to the wafers from the middle outward. Pressure applied this way allows trapped air to be pushed out as the bonding wave spreads from the center out. Starting the bonding at the center minimizes the stresses which are built up as the wafers contour to each other. The wafers have a free-state flatness of about 1 µm, while the gaps achieved in the bonding are uniform within a few nm. Thus, the wafers must distort from their free state in order to achieve this.
   1. Check the bonding by looking for interference fringes using an infrared light source and detector with a 1 µm high pass filter. Sample images are shown in Figures 4 and 5. Interference fringes (Newton rings) will appear if there is poor bonding. If bonding is good, one can proceed to step 3.3. If bonding is poor and there are nonuniformities, proceed as follows.
   2. Place the cell on an optical flat, cover with filter paper to protect and cushion the top wafer, and press the wafers together with wafer tongs. Push debonded "bubbles" to either the middle (where there is the filling hole) or to the edges. Be careful when applying force near the edges since the wafers may be slightly offset center to center. Pressure near the edges therefore may cause the top wafer to crack if it overhangs the bottom wafer.
   3. If the bonding irregularities persist or a dust particle is evident, split the wafers by wedging a razor blade between them. Repeat the process from the beginning (step 2.1.1). Up to this point, the bonding is reversible. The wafers can be rebonded at RT many times while trying to get acceptable bonding.
2. After obtaining acceptable RT bonding, one proceeds to anneal the wafers. Temperatures above 900 °C need to be reached in order to be certain of proper annealing^5,6.
   1. Stage the cell onto a quartz vacuum chuck such that the filling hole is centered over the pumping hole in the chuck. The chuck is connected to a quartz pumping tube which is used to evacuate the cell prior and during the annealing process. This tube extends outside the furnace. Evacuating the cell causes a pressure of one atmosphere to be applied to the cell. This will help with the bonding. Pumping is also necessary to prevent pressure build up if the furnace temperature is ramped up too quickly. The time it takes to significantly lower the pressure in the cell will depend on the geometry within the cell.
   2. To avoid the growth of oxide on the outside of the cell, purge the furnace chamber with a nonreacting gas, typically ⁴He, so that no oxide is grown.
   3. To allow for strains to have time to relax, it is important to ramp temperatures from 250-1,200 °C over the course of ~4 hr. After staying at 1,200 °C for at least 4 hr, turn off the furnace.
   4. Allow the system to cool to RT.
3. Analyze the cell once again using the infrared light source and detector as shown in Figure 6. If annealing went well, the cell will look as good as, or often better than, when initially put in the furnace. If there are unacceptable fringes indicating poor bonding, the entire process must be repeated from the beginning; however, this must be done with new wafers. Once annealed, the bond between wafers is permanent and there is no splitting possible.

Results

Properly bonded wafers will have no unbonded regions. Attempting to split the wafers after annealing will cause the cell to break into pieces due to the strength of the bond. Infrared images of properly bonded wafer are shown in Figures 5 and 6. Often annealing improves the uniformity of the cell, especially if local unbonded regions are due to lack of flatness in the wafers. In Figure 5 the light spots and border are bonded areas. The center bright spot is the hole for ...

Discussion

The development of suitable silicon lithography in combination with direct wafer bonding has allowed us to make vacuum tight enclosures with highly uniform small dimensions over all the full area of a 5 cm diameter silicon wafer. These enclosures have allowed us to study the behavior of liquid ⁴He in the neighborhood of its phase transitions from a normal liquid to a superfluid. These studies have verified predictions of finite-size scaling, as well as pointed out failures which remain to be explored. The work...

Materials

List of materials used in this article

Name	Company	Catalog Number	Comments
SmartCut	North American Tool	FL 130	Not much is needed per cell. Smaller sizes are available.
Silicon Wafers	Semiconductor Processing Co		There are many suppliers. Pay attention to thickness and thickness variation when ordering.
Deionized Water			General Availability
Peroxide			General Availability
Hydrochloric Acid			General Availability
Ammonium Hydroxide			General Availability
Nitrogen Gas			General Availability
Helium Gas			General Availability
Diamond Paste	Beuler Metadi II	e.g. 406533032
Diamond Drills	Starlite	e.g. 115010
Pyrex Dishes			General Availability
Filter Paper	Whatman	1001-110
Acetone			General Availability
Methanol			General Availability
Quartz tubes for flushing furnace			General Availability
Rubber vacuum hose			General Availability